Evolvable Hardware Chip for High Precision Printer Image Compression. - Hidenori Sakanashi; Mehrdad Salami; Masaya Iwata; Shogo Nakaya; Tsukasa Yamauchi; Takeshi Inuo; Nobuki Kajihara; Tetsuya Higuchi (AAAI/IAAI, 1998)

A Gate-Level EHW Chip: Implementing GA Operations and Reconfigurable Hardware on a Single LSI. - Isamu Kajitani; Tsutomu Hoshino; Daisuke Nishikawa; Hiroshi Yokoi; Shogo Nakaya; Tsukasa Yamauchi; Takeshi Inuo; Nobuki Kajihara; Masaya Iwata; Didier Keymeulen; Tetsuya Higuchi (ICES, 1998)

Mapping Algorithms for a Multi-Bit Data Path Processing Reconfigurable Chip RHW. - Tsukasa Yamauchi; Shogo Nakaya; Takeshi Inuo; Nobuki Kajihara (FCCM, 2000)

Arithmetic Operation Oriented Reconfigurable Chip: RHW. - Tsukasa Yamauchi; Shogo Nakaya; Takeshi Inuo; Nobuki Kajihara (FPL, 2001)

Techniques for Virtual Hardware on a Dynamically Reconfigurable Processor - An Approach to Tough Cases. - Hideharu Amano; Takeshi Inuo; Hirokazu Kami; Taro Fujii; Masayasu Suzuki (FPL, 2004)

An adaptive Viterbi decoder on the dynamically reconfigurable processor. - Shohei Abe; Yohei Hasegawa; Takao Toi; Takeshi Inuo; Hideharu Amano (FPT, 2006)