A CMOS bandgap reference circuit with sub-1-V operation. - Hironori Banba; Hitoshi Shiga; Akira Umezawa; Takeshi Miyaba; Toru Tanzawa; Shigeru Atsumi; Koji Sakui (IEEE J. Solid State Circuits, 1999)

A channel-erasing 1.8-V-only 32-Mb NOR flash EEPROM with a bitline direct sensing scheme. - Shigeru Atsumi; Akira Umezawa; Toru Tanzawa; Tadayuki Taura; Hitoshi Shiga; Yoshinori Takano; Takeshi Miyaba; Michiharu Matsui; Hiroshi Watanabe; Kazuaki Isobe; Shota Kitamura; Seiji Yamada; et al. (IEEE J. Solid State Circuits, 2000)

Wordline voltage generating system for low-power low-voltage flash memories. - Toru Tanzawa; Akira Umezawa; Masao Kuriyama; Tadayuki Taura; Hironori Banba; Takeshi Miyaba; Hitoshi Shiga; Yoshinori Takano; Shigeru Atsumi (IEEE J. Solid State Circuits, 2001)

A 44-mm2 four-bank eight-word page-read 64-Mb flash memory with flexible block redundancy and fast accurate word-line voltage controller. - Toru Tanzawa; Akira Umezawa; Tadayuki Taura; Hitoshi Shiga; Tokumasa Hara; Yoshinori Takano; Takeshi Miyaba; Naoya Tokiwa; Kentaro Watanabe; Hiroshi Watanabe; Kazunori Masuda; Kiyomi Naruke; et al. (IEEE J. Solid State Circuits, 2002)

A 187.5µVrms-read-noise 51mW 1.4Mpixel CMOS image sensor with PMOSCAP column CDS and 10b self-differential offset-cancelled pipeline SAR-ADC. - Jun Deguchi; Fumihiko Tachibana; Makoto Morimoto; Masayoshi Chiba; Takeshi Miyaba; Hideki Tanaka; Kyoichi Takenaka; Satoshi Funayama; Kunihiko Amano; Kazuhide Sugiura; Ryuta Okamoto; Shouhei Kousai (ISSCC, 2013)

A 2.9mW, +/- 85ppm accuracy reference clock generator based on RC oscillator with on-chip temperature calibration. - Yuji Satoh; Hiroyuki Kobayashi; Takeshi Miyaba; Shouhei Kousai (VLSIC, 2014)