A 17-ns 4-Mb CMOS DRAM. - Takeshi Nagai; Kenji Numata; Masaki Ogihara; Mitsuru Shimizu; Kimimasa Imai; Takahiko Hara; Munehiro Yoshida; Yoshikazu Saito; Yoshiaki Asao; Shizuo Sawada; Syuso Fujii (IEEE J. Solid State Circuits, 1991)

A 286 mm2 256 Mb DRAM with ×32 both-ends DQ. - Yohji Watanabe; Ring Wong; Toshiaki Kirihata; Daisuke Kato; John K. DeBrosse; Takahiko Rara; Munehiro Yoshida; Rideo Mukai; Khandker N. Quader; Takeshi Nagai; Peter Poechmueller; Peter Pfefferl; et al. (IEEE J. Solid State Circuits, 1996)

A 65nm low-power embedded DRAM with extended data-retention sleep mode. - Takeshi Nagai; Masaharu Wada; Hitoshi Iwai; Mariko Kaku; Atsushi Suzuki; Tomohisa Takai; Naoko Itoga; Takayuki Miyazaki; Hiroyuki Takenaka; Takehiko Hojo; Shinji Miyano (ISSCC, 2006)

An 833MHz Pseudo-Two-Port Embedded DRAM for Graphics Applications. - Mariko Kaku; Hitoshi Iwai; Takeshi Nagai; Masaharu Wada; Atsushi Suzuki; Tomohisa Takai; Naoko Itoga; Takayuki Miyazaki; Takayuki Iwai; Hiroyuki Takenaka; Takehiko Hojo; Shinji Miyano; et al. (ISSCC, 2008)