High-Speed CAM-Based Architecture for a Prolog Machine (ASCA). - Jiro Naganuma; Takeshi Ogura; Shin-Ichiro Yamada; Takashi Kimura (IEEE Trans. Computers, 1988)

A 20 kbit associative memory LSI for artificial intelligence machines. - Takeshi Ogura; Junzo Yamada; Shin-Ichiro Yamada; Masa'aki Tan'no (IEEE J. Solid State Circuits, 1989)

Facial image tracking system architecture utilizing real-time labeling. - Yuichi Fujino; Takeshi Ogura; Toshiaki Tsuchiya (VCIP, 1993)

High-Level Design Validation Using Algorithmic Debugging. - Jiro Naganuma; Takeshi Ogura; Tamio Hoshino (EDAC-ETC-EUROASIC, 1994)

A Highly OR-Parallel Inference Machine (Multi-ASCA) and Its Performance Evaluation: An Architecture and Its Load Balancing Algorithms. - Jiro Naganuma; Takeshi Ogura (IEEE Trans. Computers, 1994)

CAM²: A Highly-Parallel 2D Cellular Automata Architecture for Real-Time and Palm-Top Pixel-Level Image Processing. - Takeshi Ikenaga; Takeshi Ogura (Euro-Par, Vol. II, 1996)

Real-time 3D Feature Extraction Hardware Algorithm with Feature Point Matching Capability. - Eiichi Hosoya; Takeshi Ogura; Mamoru Nakanishi (MVA, 1996)

Real-time Hough Transform Based Circular Shape Extraction. - Mahmoud Méribout; Takeshi Ogura; Mamoru Nakanishi (MVA, 1996)

Real-Time Morphology Processing Using Highly Parallel 2D Cellular Automata CAM2. - Takeshi Ikenaga; Takeshi Ogura (ICIP (2), 1997)

Real-Time Line Extraction Using a Highly Parallel Hough Tranform Board. - Mamoru Nakanishi; Takeshi Ogura (ICIP (2), 1997)

Real-time 3D Reconstruction System using CAM-based Highly Parallel Processing Board. - Eiichi Hosoya; Mamoru Nakanishi; Takeshi Ogura (Three-Dimensional Image Capture and Applications, 1998)

CAM2: A Highly-Parallel Two-Dimensional Cellular Architecture. - Takeshi Ikenaga; Takeshi Ogura (IEEE Trans. Computers, 1998)

An MPEG-2 Video Encoder LSI with Scalability for HDTV based on Three-layer Cooperative Architecture. - Mitsuo Ikeda; Toshio Kondo; Koyo Nitta; Kazuhito Suguri; Takeshi Yoshitome; Toshihiro Minami; Jiro Naganuma; Takeshi Ogura (DATE, 1999)

High-speed Software-based Platform for Embedded Software of a Single-chip MPEG-2 Video Encoder LSI with HDTV Scalabilit. - Katsuyuki Ochiai; Hiroe Iwasaki; Jiro Naganuma; Makoto Endo; Takeshi Ogura (DATE, 1999)

On-Chip Multimedia Real-Time OS and its MPEG-2 Applications. - Hiroe Iwasaki; Jiro Naganuma; Makoto Endo; Takeshi Ogura (RTCSA, 1999)

A Real-Time Image Segmentation on a Massively Parallel Architecture. - Mahmoud Méribout; Mamoru Nakanishi; Takeshi Ogura (Real Time Imaging, 1999)

Concept sharing between human and interface agent under time criticality. - Tetsuo Sawaragi; Takeshi Ogura (Advanced Network Enterprises, 2000)

Global Rate Control Scheme for MPEG-2 HDTV Parallel Encoding System. - Ken Nakamura; Mitsuo Ikeda; Takeshi Yoshitome; Takeshi Ogura (ITCC, 2000)

Hough Transform Algorithm for Three-Dimensional Segment Extraction and its Parallel Hardware Implementation. - Mahmoud Méribout; Mamoru Nakanishi; Eiichi Hosoya; Takeshi Ogura (Comput. Vis. Image Underst., 2000)

A fully parallel 1-Mb CAM LSI for real-time pixel-parallel image processing. - Takeshi Ikenaga; Takeshi Ogura (IEEE J. Solid State Circuits, 2000)

Real-time CAM-based Hough transform algorithm and its performance evaluation. - Mamoru Nakanishi; Takeshi Ogura (Mach. Vis. Appl., 2000)

Real-time morphology processing using highly parallel 2-D cellular automata CAM2. - Takeshi Ikenaga; Takeshi Ogura (IEEE Trans. Image Process., 2000)

On using the CAM concept for parametric curve extraction. - Mahmoud Méribout; Takeshi Ogura; Mamoru Nakanishi (IEEE Trans. Image Process., 2000)

A parallel algorithm for real-time object recognition. - Mahmoud Méribout; Mamoru Nakanishi; Takeshi Ogura (Pattern Recognit., 2002)

Accurate and Real-time Image Processing on a New PC-compatible Board. - Mahmoud Méribout; Mamoru Nakanishi; Takeshi Ogura (Real Time Imaging, 2002)

Advanced concurrent design environment for multimedia system LSIs. - Hiroe Iwasaki; Katsuyuki Ochiai; Jiro Naganuma; Makoto Endo; Takeshi Ogura (Syst. Comput. Jpn., 2002)

A 1.296-to-5.184Gb/s Transceiver with 2.4mW/(Gb/s) Burst-mode CDR using Dual-Edge Injection-Locked Oscillator. - Kenichi Maruko; Tatsuya Sugioka; Hiroaki Hayashi; Zhiwei Zhou; Yasunori Tsukuda; Yuki Yagishita; Hironobu Konishi; Toshikyuki Ogata; Hisashi Owa; Taichi Niki; Kenji Konda; Masahiro Sato; et al. (ISSCC, 2010)

A CAM-Based Separated BTB for a Superscalar Processor. - Kosaku Fukuda; Lin Meng; Takeshi Kumaki; Takeshi Ogura (CANDAR, 2013)

Development of effective information-hiding method for embedded systems. - Kei Nakao; Kohei Hozumi; Takeshi Kumaki; Takeshi Ogura; Takeshi Fujino (MWSCAS, 2013)

Evaluation of advanced pixel-level snakes on cellular hardware platform. - Matsui Takao; Tomohiro Fujita; Tsuji Yuji; Takeshi Kumaki; Mamoru Nakanishi; Takeshi Ogura (NEWCAS, 2013)

8.2 A 12×5 two-dimensional optical I/O array for 600Gb/s chip-to-chip interconnect in 65nm CMOS. - Hiroshi Morita; Koki Uchino; Eiji Otani; Hiizu Ohtorii; Takeshi Ogura; Kazunao Oniki; Shuichi Oka; Shusaku Yanagawa; Hideyuki Suzuki (ISSCC, 2014)

Cellular automaton based pixel-level snakes. - Tomohiro Fujita; Syo Sawada; Kaihei Iwanaga; Takeshi Kumaki; Mamoru Nakanishi; Takeshi Ogura (NEWCAS, 2014)

Development of Compression Tolerable and Highly Implementable Watermarking Method for Mobile Devices. - Takeshi Kumaki; Kei Nakao; Kohei Hozumi; Takeshi Ogura; Takeshi Fujino (IEICE Trans. Inf. Syst., 2014)

Distributed Embedding Approach for Max-Plus Algebra-Based Morphological Wavelet Transform Watermarking. - Takeshi Kumaki; Tomohiro Fujita; Takeshi Ogura; P. S. Venugopala (NEWCAS, 2019)