A 250-Mb/s/pin, 1-Gb double-data-rate SDRAM with a bidirectional delay and an interbank shared redundancy scheme. - Yasuhiro Takai; Mamoru Fujita; Kyoichi Nagata; Satoshi Isa; Shigeyuki Nakazawa; Atsunori Hirobe; Hiroaki Ohkubo; Masato Sakao; Shinichi Horiba; Tadashi Fukase; Yoshihiro Takaishi; Makoto Matsuo; et al. (IEEE J. Solid State Circuits, 2000)

Improved Nagata Current Source Insensitive to Temperature and Power Supply Voltage. - Takashi Hosono; Lei Sha; Souma Yamamoto; Mayu Hirano; Takashi Ida; Anna Kuwana; Haruo Kobayashi 001; Yoichi Moroshima; Hiromichi Harakawa; Takeshi Oikawa (ISOCC, 2020)