A Processor Generation Method from Instruction Behavior Description Based on Specification of Pipeline Stages and Functional Units. - Takeshi Shiro; Masaaki Abe; Keishi Sakanushi; Yoshinori Takeuchi; Masaharu Imai (ASP-DAC, 2007)

Peak power reduction of a sensor network processor fabricated with Deeply Depleted Channel transistors in 65nm technology. - Kentaro Kawakami; Takeshi Shiro; Hironobu Yamasaki; Katsuhiro Yoda; Hiroaki Fujimoto; Kenichi Kawasaki; Yasuhiro Watanabe (ISQED, 2013)