A Single-Chip Fail-Safe Microprocessor with Memory Data Comparison Feature. - Kotaro Shimamura; Takeshi Takehara; Yosuke Shima; Kunihiko Tsunedomi (PRDC, 2006)

Measurement Results of Real Circuit Delay Degradation under Realistic Workload. - Kotaro Shimamura; Takeshi Takehara; Naohiro Ikeda (IPSJ Trans. Syst. LSI Des. Methodol., 2023)