Delay-Time Modeling for ED MOS Logic LSI. - Takeshi Tokuda; Kaoru Okazaki; Kazuhiro Sakashita; Isao Ohkura; Tatsuya Enomoto (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1983)

A Hierarchical Standard Cell Approach for Custom VLSI Design. - Takeshi Tokuda; Jiro Korematsu; Osamu Tomisawa; Sotoju Asai; Isao Ohkura; Tatsuya Enomoto (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1984)

A macrocell approach for VLSI processor design. - Takeshi Tokuda; Jiro Korematsu; Yukihiko Shimazu; Narumi Sakashita; Tohru Kengaku; Toshiki Fugiyama; Takio Ohno; Osamu Tomisawa (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

Built-in self-test in a 24 bit floating point digital signal processor. - Narumi Sakashita; Hisako Sawai; Eiichi Teraoka; Toshiki Fugiyama; Toru Kengaku; Yukihiko Shimazu; Takeshi Tokuda (ITC, 1990)

A 100-mega-access per second matching memory for a data-driven microprocessor. - Hidehiro Takata; Shinji Komori; Toshiyuki Tamura; Fumiyasu Asai; Hisakazu Sato; Takio Ohno; Takeshi Tokuda; Hiroki Nishikawa; Hirofumi Terada (IEEE J. Solid State Circuits, 1990)

A Data-Driven Architecture for Distributed Parallel Processing. - Toshiyuki Tamura; Shinji Komori; Fumiyasu Asai; Hirono Tsubota; Hisakazu Sato; Hidehiro Takata; Yoshihiro Seguchi; Takeshi Tokuda; Hiroaki Terada (ICCD, 1991)

A Built-in Self- Test for ADC and DAC in a Single-Chip Speech CODEC. - Eiichi Teraoka; Toru Kengaku; Ikuo Yasui; Kazuyuki Ishikawa; Takahiro Matsuo; Hideyuki Wakada; Narumi Sakashita; Yukihiko Shimazu; Takeshi Tokuda (ITC, 1993)

Fuzzy inference and fuzzy inference processor. - Kazuo Nakamura; Narumi Sakashita; Yasuhiko Nitta; Ken'ichi Shimomura; Takeshi Tokuda (IEEE Micro, 1993)