A fourth-order bandpass Δ-Σ modulator using second-order bandpass noise-shaping dynamic element matching. - Takeshi Ueno; Akira Yasuda; Takafumi Yamaji; Tetsuro Itakura (IEEE J. Solid State Circuits, 2002)

A 1.2-V, 12-bit, 200M sample/s current-steering D/A converter in 90-nm CMOS. - Takeshi Ueno; Takafumi Yamaji; Tetsuro Itakura (CICC, 2005)

A 10-bit, 200-MSPS, 105-mW pipeline A-to-D converter. - Tomohiko Ito; Takeshi Ueno; Daisuke Kurose; Takafumi Yamaji; Tetsuro Itakura (IEICE Electron. Express, 2005)

A 0.9 V 1.5 mW Continuous-Time Modulator for W-CDMA. - Takeshi Ueno; Tetsuro Itakura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

Balanced 3-phase analog signal processing for radio communications. - Takafumi Yamaji; Tetsuro Itakura; Rui Ito; Takeshi Ueno; Hidenori Okuni (ISCAS, 2006)

Low-Power Design of 10-bit 80-MSPS Pipeline ADCs. - Tomohiko Ito; Daisuke Kurose; Takeshi Ueno; Takafumi Yamaji; Tetsuro Itakura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

55-mW 200-MSPS 10-bit pipeline ADCs for wireless receivers. - Daisuke Kurose; Tomohiko Ito; Takeshi Ueno; Takafumi Yamaji; Tetsuro Itakura (IEEE J. Solid State Circuits, 2006)

A 1.2-V, 12-bit, 200 MSample/s Current-Steering D/A Converter in 90-nm CMOS. - Takeshi Ueno; Takafumi Yamaji; Tetsuro Itakura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

An area-efficient sampling rate converter using negative feedback technique. - Masanori Furuta; Takafumi Yamaji; Takeshi Ueno; Tetsuro Itakura (ISCAS, 2008)

55-mW, 1.2-V, 12-bit, 100-MSPS Pipeline ADCs for Wireless Receivers. - Tomohiko Ito; Daisuke Kurose; Takeshi Ueno; Takafumi Yamaji; Tetsuro Itakura (IEICE Trans. Electron., 2008)

1.2 V, 24 mW/ch, 10 bit, 80 MSample/s Pipelined A/D Converters. - Takeshi Ueno; Tomohiko Ito; Daisuke Kurose; Takafumi Yamaji; Tetsuro Itakura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

A Direct Conversion Receiver Adopting Balanced Three-Phase Analog System. - Takafumi Yamaji; Takeshi Ueno; Tetsuro Itakura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

Modeling Patent Quality: A System for Large-scale Patentability Analysis using Text Mining. - Shohei Hido; Shoko Suzuki; Risa Nishiyama; Takashi Imamichi; Rikiya Takahashi; Tetsuya Nasukawa; Tsuyoshi Idé; Yusuke Kanehira; Rinju Yohda; Takeshi Ueno; Akira Tajima; Toshiya Watanabe (J. Inf. Process., 2012)

20 mV input, 4.2 V output SIDO boost converter with low-power controller and adaptive switch size selector for thermoelectric energy harvesting. - Yosuke Toyama; Taichi Ogawa; Takeshi Ueno; Tetsuro Itakura (A-SSCC, 2016)

A 4.5V/ns Active Slew-Rate-Controlling Gate Driver with Robust Discrete-Time Feedback Technique for 600V Superjunction MOSFETs. - Shusuke Kawai; Takeshi Ueno; Kohei Onizuka (ISSCC, 2019)

An Active Slew Rate Control Gate Driver IC With Robust Discrete-Time Feedback Technique for 600-V Superjunction MOSFETs. - Shusuke Kawai; Takeshi Ueno; Hiroki Ishikuro; Kohei Onizuka (IEEE J. Solid State Circuits, 2023)