Efficient Algorithms for Channel Routing. - Takeshi Yoshimura; Ernest S. Kuh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1982)

An efficient channel router. - Takeshi Yoshimura (DAC, 1984)

Compaction-Based Custom LSI Layout Design Method. - Masaki Ishikawa; Tsuneo Matsuda; Takeshi Yoshimura; Satoshi Goto (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987)

A single chip VLSI chrominance/luminance separator based on a silicon compiler. - Takashi Miyazaki; Takao Nishitani; Shinichi Aikoh; Masaki Ishikawa; Takeshi Yoshimura; Kaoru Mitsuhashi; M. Furuichi (ICASSP, 1989)

A resource sharing and control synthesis method for conditional branches. - Kazutoshi Wakabayashi; Takeshi Yoshimura (ICCAD, 1989)

A rule-based and algorithmic approach for logic synthesis. - Takeshi Yoshimura (Future Gener. Comput. Syst., 1989)

New Placement and Global Routing Algorithms for Standard Cell Layouts. - Masato Edahiro; Takeshi Yoshimura (DAC, 1990)

A Multi-Layer Channel Router with New Style of Over-the-Cell Routing. - Takashi Fujii; Yoko Mima; Tsuneo Matsuda; Takeshi Yoshimura (DAC, 1992)

A Partitioning-Based Logic Optimization Method for Large Scale Circuits with Boolean Matrix. - Yuichi Nakamura 002; Takeshi Yoshimura (DAC, 1995)

An O-Tree Representation of Non-Slicing Floorplan and Its Applications. - Pei-Ning Guo; Chung-Kuan Cheng; Takeshi Yoshimura (DAC, 1999)

An enhanced perturbing algorithm for floorplan design using the O-tree representation. - Yingxin Pang; Chung-Kuan Cheng; Takeshi Yoshimura (ISPD, 2000)

Floorplanning using a tree representation. - Pei-Ning Guo; Toshihiko Takahashi; Chung-Kuan Cheng; Takeshi Yoshimura (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

RObust Header Compression (ROHC): Framework and four profiles: RTP, UDP, ESP, and uncompressed. - Carsten Bormann; Carsten Burmeister; Mikael Degermark; Hideaki Fukushima; Hans Hannu; Lars-Erik Jonsson; Rolf Hakenberg; Tmima Koren; Khiem Le; Zhigang Liu 010; Anton Martensson; Akihiro Miyazaki; et al. (RFC, 2001)

Streaming agent for wired network/wireless link rate-mismatch environment. - Gene Cheung; Wai-tian Tan; Takeshi Yoshimura (IEEE Workshop on Multimedia Signal Processing, 2002)

Rate and robustness control with RTP monitoring agent for mobile multimedia streaming. - Takeshi Yoshimura; Tomoyuki Ohya; Toshiro Kawahara; Minoru Etoh (ICC, 2002)

Rate-distortion optimized application-level retransmission using streaming agent for video streaming over 3G wireless network. - Gene Cheung; Wai-tian Tan; Takeshi Yoshimura (ICIP (1), 2002)

Mobile streaming media CDN enabled by dynamic SMIL. - Takeshi Yoshimura; Yoshifumi Yonemoto; Tomoyuki Ohya; Minoru Etoh; Susie J. Wee (WWW, 2002)

A Minimum Bandwidth Guaranteed Service Model and Its Implementation on Wireless Packet Scheduler. - Moo Ryong Jeong; Takeshi Yoshimura; Hiroyuki Morikawa; Tomonori Aoyama (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

Multiple-Reference Compression of RTP/UDP/IP Headers for Mobile Multimedia Communications. - Takeshi Yoshimura; Toshiro Kawahara; Tomoyuki Ohya; Minoru Etoh (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

End-to-end robust IP soft handover. - Hosei Matsuoka; Takeshi Yoshimura; Tomoyuki Ohya (ICC, 2003)

A System Architecture for Managing Mobile Streaming Media Service. - Sumit Roy 002; Michele Covell; John Ankcorn; Susie J. Wee; Takeshi Yoshimura (ICDCS Workshops, 2003)

A Robust Method for Soft IP Handover. - Hosei Matsuoka; Takeshi Yoshimura; Tomoyuki Ohya (IEEE Internet Comput., 2003)

Timing optimization by replacing flip-flops to latches. - Ko Yoshikawa; Yasuhiko Hagihara; Keisuke Kanamaru; Yuichi Nakamura 002; Shigeto Inui; Takeshi Yoshimura (ASP-DAC, 2004)

A fast hardware/software co-verification method for system-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communication. - Yuichi Nakamura 002; Kohei Hosokawa; Ichiro Kuroda; Ko Yoshikawa; Takeshi Yoshimura (DAC, 2004)

Double feedback streaming agent for real-time delivery of media over 3G wireless networks. - Gene Cheung; Wai-tian Tan; Takeshi Yoshimura (IEEE Trans. Multim., 2004)

A fast chip-scale power estimation method for large and complex LSIs based on hierarchical analysis. - Yuichi Nakamura 002; Takeshi Yoshimura (ISCAS (1), 2005)

An Engineering Change Orders Design Method Based on Patchwork-Like Partitioning for High Performance LSIs. - Yuichi Nakamura 002; Ko Yoshikawa; Takeshi Yoshimura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

Advances in Wireless Video Delivery. - Minoru Etoh; Takeshi Yoshimura (Proc. IEEE, 2005)

Real-time video transport optimization using streaming agent over 3G wireless networks. - Gene Cheung; Wai-tian Tan; Takeshi Yoshimura (IEEE Trans. Multim., 2005)

Wireless video applications in 3G and beyond. - Minoru Etoh; Takeshi Yoshimura (IEEE Wirel. Commun., 2005)

On the Number of 3-D IC Floorplan Configurations and a Solution Perturbation Method with Good Convergence. - Song Chen 001; Takeshi Yoshimura (APCCAS, 2006)

Realizability of Score Sequence Pair of an (r1l, r12, r22)-Tournament. - Masaya Takahashi; Takahiro Watanabe; Takeshi Yoshimura (APCCAS, 2006)

Hierarchical-Analysis-Based Fast Chip-Scale Power Estimation Method for Large and Complex LSIs. - Yuichi Nakamura 002; Takeshi Yoshimura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

Domino Logic Synthesis System and its Applications. - Ko Yoshikawa; Shigeto Inui; Yasuhiko Hagihara; Yuichi Nakamura 002; Takeshi Yoshimura (J. Circuits Syst. Comput., 2006)

Construction of an (r11, r12, r22)-Tournament from a Score Sequence Pair. - Masaya Takahashi; Takahiro Watanabe; Takeshi Yoshimura (ISCAS, 2007)

A stable fixed-outline floorplanning method. - Song Chen 001; Takeshi Yoshimura (ISPD, 2007)

Max-Flow Scheduling in High-Level Synthesis. - Liangwei Ge; Song Chen 001; Kazutoshi Wakabayashi; Takashi Takenaka; Takeshi Yoshimura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

Score Sequence Pair Problems of (r11, r12, r22)-Tournaments - - Determination of Realizability - - . - Masaya Takahashi; Takahiro Watanabe; Takeshi Yoshimura (IEICE Trans. Inf. Syst., 2007)

Acoustic OFDM: Embedding High Bit-Rate Data in Audio. - Hosei Matsuoka; Yusuke Nakashima; Takeshi Yoshimura; Toshiro Kawahara (MMM, 2008)

Acoustic OFDM System and Performance Analysis. - Hosei Matsuoka; Yusuke Nakashima; Takeshi Yoshimura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Data Transmission on AM Broadcast with Acoustic OFDM. - Yusuke Nakashima; Hosei Matsuoka; Takeshi Yoshimura; Hiroshi Miura; Seiichi Nakajima; Masanori Machida; Gen-Ichiro Ohta (IEICE Trans. Commun., 2008)

A Synthesis Method of General Floating-Point Arithmetic Units by Aligned Partition. - Liangwei Ge; Song Chen 001; Yuichi Nakamura 002; Takeshi Yoshimura (IPSJ Trans. Syst. LSI Des. Methodol., 2008)

Fixed-Outline Floorplanning: Block-Position Enumeration and a New Method for Calculating Area Costs. - Song Chen 001; Takeshi Yoshimura (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Register placement for high-performance circuits. - Mei-Fang Chiang; Takumi Okamoto; Takeshi Yoshimura (DATE, 2009)

A generalized V-shaped multilevel method for large scale floorplanning. - Song Chen 001; Zheng Xu; Takeshi Yoshimura (ISQED, 2009)

Lagrangian relaxation based register placement for high-performance circuits. - Mei-Fang Chiang; Takumi Okamoto; Takeshi Yoshimura (ISQED, 2009)

Performance enhancement of TFI-OFDM with path selection based channel identification. - Takeshi Yoshimura; Chang-Jun Ahn; Takeshi Kamio; Hisato Fujisaka; Kazuhisa Haeiwa (Digit. Signal Process., 2009)

Lagrangian Relaxation Based Inter-Layer Signal Via Assignment for 3-D ICs. - Song Chen 001; Liangwei Ge; Mei-Fang Chiang; Takeshi Yoshimura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Exploration of Schedule Space by Random Walk. - Liangwei Ge; Song Chen 001; Takeshi Yoshimura (IPSJ Trans. Syst. LSI Des. Methodol., 2009)

Acoustic OFDM system and its extension. - Hosei Matsuoka; Yusuke Nakashima; Takeshi Yoshimura (Vis. Comput., 2009)

Post-scheduling frequency assignment for energy-efficient high-level synthesis. - Ru Liu; Song Chen 001; Takeshi Yoshimura (APCCAS, 2010)

Whitespace insertion for through-silicon via planning on 3-D SoCs. - Wei Zhong; Song Chen 001; Takeshi Yoshimura (ISCAS, 2010)

Redundant via Insertion: Removing Design Rule Conflicts and Balancing via Density. - Song Chen 001; Jianwei Shen 003; Wei Guo; Mei-Fang Chiang; Takeshi Yoshimura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

Multi-layer floorplanning for stacked ICs: Configuration number and fixed-outline constraints. - Song Chen 001; Takeshi Yoshimura (Integr., 2010)

Mobility overlap-removal based timing-constrained scheduling. - Song Chen 001; Yuan Yao; Takeshi Yoshimura (ASICON, 2011)

An effecient level-shifter floorplanning method for Multi-voltage design. - Xiaolin Zhang; Zhi Lin; Song Chen 001; Takeshi Yoshimura (ASICON, 2011)

A low power technology mapping method for Adaptive Logic Module. - Wei Chen; Xiaolin Zhang; Takeshi Yoshimura; Yuichi Nakamura 002 (FPT, 2011)

Hypothesis Preservation Approach to Scene Text Recognition with Weighted Finite-State Transducer. - Takafumi Yamazoe; Minoru Etoh; Takeshi Yoshimura; Kousuke Tsujino (ICDAR, 2011)

Floorplanning driven Network-on-Chip synthesis for 3-D SoCs. - Wei Zhong; Song Chen 001; Fei Ma; Takeshi Yoshimura; Satoshi Goto (ISCAS, 2011)

Application-specific Network-on-Chip synthesis: Cluster generation and network component insertion. - Wei Zhong; Bei Yu 001; Song Chen 001; Takeshi Yoshimura; Sheqin Dong; Satoshi Goto (ISQED, 2011)

Can Linux be Rejuvenated without Reboots? - Takeshi Yoshimura; Hiroshi Yamada; Kenji Kono (WoSAR@ISSRE, 2011)

Wirelength driven I/O buffer placement for flip-chip with timing-constrained. - Nan Liu 002; Shiyu Liu; Takeshi Yoshimura (APCCAS, 2012)

Is Linux Kernel Oops Useful or Not? - Takeshi Yoshimura; Hiroshi Yamada; Kenji Kono (HotDep, 2012)

Practically scalable floorplanning with voltage island generation. - Song Chen 001; Xiaolin Zhang; Takeshi Yoshimura (ISLPED, 2012)

Application-Specific Network-on-Chip synthesis with topology-aware floorplanning. - Bo Huang; Song Chen 001; Wei Zhong; Takeshi Yoshimura (SBCCI, 2012)

Port assignment for interconnect reduction in high-level synthesis. - Cong Hao; Song Chen 001; Takeshi Yoshimura (VLSI-DAT, 2012)

Floorplanning for High Utilization of Heterogeneous FPGAs. - Nan Liu 002; Song Chen 001; Takeshi Yoshimura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

Cluster Generation and Network Component Insertion for Topology Synthesis of Application-Specific Network-on-Chips. - Wei Zhong; Takeshi Yoshimura; Bei Yu 001; Song Chen 001; Sheqin Dong; Satoshi Goto (IEICE Trans. Electron., 2012)

Genetic Algorithm based pipeline scheduling in high-level synthesis. - Xiaohao Gao; Takeshi Yoshimura (ASICON, 2013)

Interconnection allocation between functional units and registers in High-Level Synthesis. - Cong Hao; Nan Wang 003; Song Chen 001; Takeshi Yoshimura; Min-You Wu (ASICON, 2013)

Timing and resource constrained leakage power aware scheduling in high-level synthesis. - Nan Wang 003; Cong Hao; Nan Liu 002; Haoran Zhang; Takeshi Yoshimura (ASICON, 2013)

Power and resource aware scheduling with multiple voltages. - Haoran Zhang; Cong Hao; Nan Wang 003; Song Chen 001; Takeshi Yoshimura (ASICON, 2013)

Lagrangian relaxation based pin assignment and Through-Silicon Via planning for 3-D SoCs. - Wei Zhong; Song Chen 001; Yang Geng; Takeshi Yoshimura (ASICON, 2013)

Network simplex method based Multiple Voltage Scheduling in Power-efficient High-level synthesis. - Cong Hao; Song Chen 001; Takeshi Yoshimura (ASP-DAC, 2013)

Topology-aware floorplanning for 3D application-specific Network-on-Chip synthesis. - Bo Huang; Song Chen 001; Wei Zhong; Takeshi Yoshimura (ISCAS, 2013)

Mobility overlap-removal based leakage power aware scheduling in high-level synthesis. - Nan Wang 003; Song Chen 001; Yuhuan Sun; Takeshi Yoshimura (ISCAS, 2013)

Min-cut based leakage power aware scheduling in high-level synthesis. - Nan Wang 003; Song Chen 001; Takeshi Yoshimura (ISQED, 2013)

Resource-Aware Multi-Layer Floorplanning for Partially Reconfigurable FPGAs. - Nan Liu 002; Song Chen 001; Takeshi Yoshimura (IEICE Trans. Electron., 2013)

Floorplanning and Topology Synthesis for Application-Specific Network-on-Chips. - Wei Zhong; Song Chen 001; Bo Huang; Takeshi Yoshimura; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Using Fault Injection to Analyze the Scope of Error Propagation in Linux. - Takeshi Yoshimura; Hiroshi Yamada; Kenji Kono (Inf. Media Technol., 2013)

Integration of Push-Based and Pull-Based Connectivity Status Sharing for Efficient Data Forwarding towards Mobile Sinks in Wireless Sensor Networks. - Takeshi Yoshimura; Kazuya Murao; Akimitsu Kanzaki; Shojiro Nishio (AINA, 2014)

Who Writes What Checkers? - Learning from Bug Repositories. - Takeshi Yoshimura; Kenji Kono (HotDep, 2014)

Do Injected Faults Cause Real Failures? A Case Study of Linux. - Nobuo Kikuchi; Takeshi Yoshimura; Ryo Sakuma; Kenji Kono (ISSRE Workshops, 2014)

Unified VLSI Architecture of Motion Vector and Boundary Strength Parameter Decoder for 8K UHDTV HEVC Decoder. - Shihao Wang; Dajiang Zhou; Jian-Bin Zhou; Takeshi Yoshimura; Satoshi Goto (PCM, 2014)

FoxyFeed: Forging Device-Level Asynchronous Events for Kernel Development. - Kenji Kono; Shunsuke Miyahara; Hiroshi Yamada; Takeshi Yoshimura (PRDC, 2014)

Leakage Power Aware Scheduling in High-Level Synthesis. - Nan Wang 003; Song Chen 001; Cong Hao; Haoran Zhang; Takeshi Yoshimura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

Mobility Overlap-Removal-Based Leakage Power and Register-Aware Scheduling in High-Level Synthesis. - Nan Wang 003; Song Chen 001; Wei Zhong; Nan Liu 002; Takeshi Yoshimura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

Simultaneous scheduling and binding for resource usage and interconnect complexity reduction in high-level synthesis. - Cong Hao; Jianmo Ni; Hui-Tong Wang; Takeshi Yoshimura (ASICON, 2015)

Primal-dual method based simultaneous functional unit and register binding. - Jianmo Ni; Cong Hao; Nan Wang 003; Qian Ai; Takeshi Yoshimura (ASICON, 2015)

Tabu search based multiple voltage scheduling under both timing and resource constraints. - Jianmo Ni; Nan Wang 003; Takeshi Yoshimura (ISQED, 2015)

Unified Parameter Decoder Architecture for H.265/HEVC Motion Vector and Boundary Strength Decoding. - Shihao Wang; Dajiang Zhou; Jian-Bin Zhou; Takeshi Yoshimura; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

High Performance VLSI Architecture of H.265/HEVC Intra Prediction for 8K UHDTV Video Decoder. - Jian-Bin Zhou; Dajiang Zhou; Shihao Wang; Takeshi Yoshimura; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

Power-efficient partitioning and cluster generation design for application-specific Network-on-Chip. - Jiayi Ma 002; Cong Hao; Wencan Zhang; Takeshi Yoshimura (ISOCC, 2016)

14.7 A 4Gpixel/s 8/10b H.265/HEVC video decoder chip for 8K Ultra HD applications. - Dajiang Zhou; Shihao Wang; Heming Sun; Jian-Bin Zhou; Jiayi Zhu 001; Yijin Zhao; Jinjia Zhou; Shuping Zhang; Shinji Kimura; Takeshi Yoshimura; Satoshi Goto (ISSCC, 2016)

Economical smart home scheduling for single and multiple users. - Cong Hao; Takeshi Yoshimura (MWSCAS, 2016)

Thermal-aware floorplanning for NoC-sprinting. - Hui Zhu; Cong Hao; Takeshi Yoshimura (MWSCAS, 2016)

An efficient algorithm for 3D-IC TSV assignment. - Cong Hao; Nan Ding; Takeshi Yoshimura (NEWCAS, 2016)

A Case for Static Analysis of Linux to Find Faults in Interrupt Request Handlers. - Takeshi Yoshimura; Kenji Kono (J. Inf. Process., 2016)

Leakage-Power-Aware Scheduling With Dual-Threshold Voltage Design. - Nan Wang 003; Wei Zhong; Cong Hao; Song Chen 001; Takeshi Yoshimura; Yu Zhu 005 (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A force directed partitioning algorithm for 3D floorplanning. - Linquan Lyu; Takeshi Yoshimura (ASICON, 2017)

Application of on-line machine learning in optimization algorithms: A case study for local search. - Cong Hao; Takeshi Yoshimura (CEEC, 2017)

Chain-NN: An energy-efficient 1D chain architecture for accelerating deep convolutional neural networks. - Shihao Wang; Dajiang Zhou; Xushen Han; Takeshi Yoshimura (DATE, 2017)

Energy-efficient scheduling method with cross-loop model for resource-limited CNN accelerator designs. - Kaiyi Yang; Shihao Wang; Jian-Bin Zhou; Takeshi Yoshimura (ISCAS, 2017)

Measurement-domain intra prediction framework for compressively sensed images. - Jian-Bin Zhou; Dajiang Zhou; Li Guo 006; Takeshi Yoshimura; Satoshi Goto (ISCAS, 2017)

Approximate-DCT-derived measurement matrices for compressed sensing. - Jian-Bin Zhou; Dajiang Zhou; Takeshi Yoshimura; Satoshi Goto (ISCAS, 2017)

A particle swarm optimization and branch and bound based algorithm for economical smart home scheduling. - Yangyizhou Wang; Cong Hao; Takeshi Yoshimura (MWSCAS, 2017)

3D-IC signal TSV assignment for thermal and wirelength optimization. - Yuxin Qian; Cong Hao; Takeshi Yoshimura (PATMOS, 2017)

Real-Time UHD Background Modelling with Mixed Selection Block Updates. - Axel Beaugendre; Satoshi Goto; Takeshi Yoshimura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

An Efficient Multi-Level Algorithm for 3D-IC TSV Assignment. - Cong Hao; Takeshi Yoshimura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

Framework and VLSI Architecture of Measurement-Domain Intra Prediction for Compressively Sensed Visual Contents. - Jian-Bin Zhou; Dajiang Zhou; Li Guo 006; Takeshi Yoshimura; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

An 8K H.265/HEVC Video Decoder Chip With a New System Pipeline Design. - Dajiang Zhou; Shihao Wang; Heming Sun; Jian-Bin Zhou; Jiayi Zhu 001; Yijin Zhao; Jinjia Zhou; Shuping Zhang; Shinji Kimura; Takeshi Yoshimura; Satoshi Goto (IEEE J. Solid State Circuits, 2017)

A Unified Scheduling Approach for Power and Resource Optimization With Multiple Vdd or/and Vth in High-Level Synthesis. - Cong Hao; Nan Wang 003; Takeshi Yoshimura (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

VLSI Implementation of HEVC Motion Compensation With Distance Biased Direct Cache Mapping for 8K UHDTV Applications. - Shihao Wang; Dajiang Zhou; Jian-Bin Zhou; Takeshi Yoshimura; Satoshi Goto (IEEE Trans. Circuits Syst. Video Technol., 2017)

Interconnection Allocation Between Functional Units and Registers in High-Level Synthesis. - Cong Hao; Jianmo Ni; Nan Wang 003; Takeshi Yoshimura (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation for 8k Ultra-HD TV Encoding. - Jian-Bin Zhou; Dajiang Zhou; Shihao Wang; Shuping Zhang; Takeshi Yoshimura; Satoshi Goto (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Towards Selecting Best Combination of SQL-on-Hadoop Systems and JVMs. - Tatsuhiro Chiba; Takeshi Yoshimura; Michihiro Horie; Hiroshi Horii (IEEE CLOUD, 2018)

Column Cache: Buffer Cache for Columnar Storage on HDFS. - Takeshi Yoshimura; Tatsuhiro Chiba; Hiroshi Horii (IEEE BigData, 2018)

Refinement of Utterance Database and Concatenation of Utterances for Enhancing System Utterances in Chat-oriented Dialogue System. - Yuiko Tsunomori; Ryuichiro Higashinaka; Takeshi Yoshimura (LaCATODA@IJCAI, 2018)

Economical Smart Home Scheduling by Cuckoo Search optimization via Levy Flight. - Rujie Lai; Yangyizhou Wang; Cong Hao; Takeshi Yoshimura (MWSCAS, 2018)

TSV Assignment of Thermal and Wirelength Optimization for 3D-IC Routing. - Yi Zhao; Cong Hao; Takeshi Yoshimura (PATMOS, 2018)

Approximate-DCT-Derived Measurement Matrices with Row-Operation-Based Measurement Compression and its VLSI Architecture for Compressed Sensing. - Jian-Bin Zhou; Dajiang Zhou; Takeshi Yoshimura; Satoshi Goto (IEICE Trans. Electron., 2018)

EvFS: User-level, Event-Driven File System for Non-Volatile Memory. - Takeshi Yoshimura; Tatsuhiro Chiba; Hiroshi Horii (HotStorage, 2019)

Chat-Oriented Dialogue System That Uses User Information Acquired Through Dialogue and Its Long-Term Evaluation. - Yuiko Tsunomori; Ryuichiro Higashinaka; Takeshi Yoshimura; Yoshinori Isoda (IWSDS, 2019)

ImageJockey: A Framework for Container Performance Engineering. - Takeshi Yoshimura; Rina Nakazawa; Tatsuhiro Chiba (CLOUD, 2020)

Investigating Genome Analysis Pipeline Performance on GATK with Cloud Object Storage. - Tatsuhiro Chiba; Takeshi Yoshimura (MASCOTS, 2020)

Deep Neural Network Incorporating CNN and MF for Item-Based Fashion Recommendation. - Taku Ito; Issei Nakamura; Shigeki Tanaka; Toshiki Sakai; Takeshi Kato; Yusuke Fukazawa; Takeshi Yoshimura (PKAW, 2020)

MicroLens: A Performance Analysis Framework for Microservices Using Hidden Metrics With BPF. - Marcelo Amaral; Tatsuhiro Chiba; Scott Trent; Takeshi Yoshimura; Sunyanan Choochotkaew (CLOUD, 2022)

AutoDECK: Automated Declarative Performance Evaluation and Tuning Framework on Kubernetes. - Sunyanan Choochotkaew; Tatsuhiro Chiba; Scott Trent; Takeshi Yoshimura; Marcelo Amaral (CLOUD, 2022)

Objcache: An Elastic Filesystem over External Persistent Storage for Container Clusters. - Takeshi Yoshimura; Tatsuhiro Chiba; Sunyanan Choochotkaew; Seetharami Seelam; Hui-Fang Wen; Jonas Pfefferle (CoRR, 2023)

The infrastructure powering IBM's Gen AI model development. - Talia Gershon; Seetharami Seelam; Brian Belgodere; Milton Bonilla; Lan Hoang; Danny Barnett; I-Hsin Chung; Apoorve Mohan; Ming-Hung Chen; Lixiang Luo; Robert Walkup; Constantinos Evangelinos; et al. (CoRR, 2024)

Speeding up Model Loading with fastsafetensors. - Takeshi Yoshimura; Tatsuhiro Chiba; Manish Sethi; Daniel Waddington; Swaminathan Sundararaman (CoRR, 2025)