A macrocell approach for VLSI processor design. - Takeshi Tokuda; Jiro Korematsu; Yukihiko Shimazu; Narumi Sakashita; Tohru Kengaku; Toshiki Fugiyama; Takio Ohno; Osamu Tomisawa (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

An elastic pipeline mechanism by self-timed circuits. - Shinji Komori; Hidehiro Takata; Toshiyuki Tamura; Fumiyasu Asai; Takio Ohno; Osamu Tomisawa; Tetsuo Yamasaki; Kenji Shima; Katsuhiko Asada; Hiroaki Terada (IEEE J. Solid State Circuits, 1988)

VLSI implementation of a variable-length pipeline scheme for data-driven processors. - Tetsuo Yamasaki; Kenji Shima; Shinji Komori; Hidehiro Takata; Toshiyuki Tamura; Fumiyasu Asai; Takio Ohno; Osamu Tomisawa; Hiroaki Terada (IEEE J. Solid State Circuits, 1989)

A 40-MFLOPS 32-bit floating-point processor with elastic pipeline scheme. - Shinji Komori; Hidehiro Takata; Todhixuki Tamura; Fumixsdu Asai; Takio Ohno; Osamu Tomisawa; Tetsuo Yamasaki; Kenji Shima; Hiroaki Nishikawa; Hiroaki Terada (IEEE J. Solid State Circuits, 1989)

A 400 K-transistor CMOS sea-of-gates array with continuous track allocation. - Masatomi Okabe; Yoshihiro Okuno; Takahiko Arakawa; Ichiro Tomioka; Takio Ohno; Tomoyoshi Noda; Masahiro Hatanaka; Yoichi Kuramitsu (IEEE J. Solid State Circuits, 1989)

A 100-mega-access per second matching memory for a data-driven microprocessor. - Hidehiro Takata; Shinji Komori; Toshiyuki Tamura; Fumiyasu Asai; Hisakazu Sato; Takio Ohno; Takeshi Tokuda; Hiroki Nishikawa; Hirofumi Terada (IEEE J. Solid State Circuits, 1990)