Configurable multi-processor architecture and its processor element design. - Tsutomu Nishimura; Takuji Miki; Hiroaki Sugiura 003; Yuki Matsumoto; Masatsugu Kobayashi; Toshiyuki Kato; Tsutomu Eda; Hironori Yamauchi (ASP-DAC, 2006)

Design methods for pipeline & delta-sigma A-to-D converters with convex optimization. - Kazuo Matsukawa; Takashi Morie; Yusuke Tokunaga; Shiro Sakiyama; Yosuke Mitani; Masao Takayama; Takuji Miki; Akinori Matsumoto; Koji Obata; Shiro Dosho (ASP-DAC, 2009)

An 11-b 300-MS/s Double-Sampling Pipelined ADC With On-Chip Digital Calibration for Memory Effects. - Takuji Miki; Takashi Morie; Toshiaki Ozeki; Shiro Dosho (IEEE J. Solid State Circuits, 2012)

A 71dB-SNDR 50MS/s 4.2mW CMOS SAR ADC by SNR enhancement techniques utilizing noise. - Takashi Morie; Takuji Miki; Kazuo Matsukawa; Yoji Bando; Takeshi Okumoto; Koji Obata; Shiro Sakiyama; Shiro Dosho (ISSCC, 2013)

12.4 A 1mm-pitch 80×80-channel 322Hz-frame-rate touch sensor with two-step dual-mode capacitance scan. - Noriyuki Miura; Shiro Dosho; Satoshi Takaya; Daisuke Fujimoto; Takuya Kiriyama; Hiroyuki Tezuka; Takuji Miki; Hiroto Yanagawa; Makoto Nagata (ISSCC, 2014)

A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques. - Takuji Miki; Takashi Morie; Kazuo Matsukawa; Yoji Bando; Takeshi Okumoto; Koji Obata; Shiro Sakiyama; Shiro Dosho (IEEE J. Solid State Circuits, 2015)

A 1 mm Pitch 80 × 80 Channel 322 Hz Frame-Rate Multitouch Distribution Sensor With Two-Step Dual-Mode Capacitance Scan. - Noriyuki Miura; Shiro Dosho; Hiroyuki Tezuka; Takuji Miki; Daisuke Fujimoto; Takuya Kiriyama; Makoto Nagata (IEEE J. Solid State Circuits, 2015)

A 2GS/s 8b time-interleaved SAR ADC for millimeter-wave pulsed radar baseband SoC. - Takuji Miki; Toshiaki Ozeki; Jun-ichi Naka (A-SSCC, 2016)

A 500MHz-BW -52.5dB-THD Voltage-to-Time Converter utilizing a two-step transition inverter. - Takuji Miki; Noriyuki Miura; Kento Mizuta; Shiro Dosho; Makoto Nagata (ESSCIRC, 2016)

A 97.99 dB SNDR, 2 kHz BW, 37.1 µW noise-shaping SAR ADC with dynamic element matching and modulation dither effect. - Koji Obata; Kazuo Matsukawa; Takuji Miki; Yusuke Tsukamoto; Koji Sushihara (VLSI Circuits, 2016)

A 500 MHz-BW -52.5 dB-THD Voltage-to-Time Converter Utilizing Two-Step Transition Inverter Delay Lines in 28 nm CMOS. - Takuji Miki; Noriyuki Miura; Kento Mizuta; Shiro Dosho; Makoto Nagata (IEICE Trans. Electron., 2017)

A 2-GS/s 8-bit Time-Interleaved SAR ADC for Millimeter-Wave Pulsed Radar Baseband SoC. - Takuji Miki; Toshiaki Ozeki; Jun-ichi Naka (IEEE J. Solid State Circuits, 2017)

Over-the-top Si Interposer Embedding Backside Buried Metal PDN to Reduce Power Supply Impedance of Large Scale Digital ICs. - Takuji Miki; Makoto Nagata; Akihiro Tsukioka; Noriyuki Miura; Takaaki Okidono; Yuuki Araga; Naoya Watanabe; Haruo Shimamoto; Katsuya Kikuchi (3DIC, 2019)

On-Chip Physical Attack Protection Circuits for Hardware Security : Invited Paper. - Makoto Nagata; Takuji Miki; Noriyuki Miura (CICC, 2019)

A 0.72pJ/bit 400μm2 Physical Random Number Generator Utilizing SAR Technique for Secure Implementation on Sensor Nodes. - Takuji Miki; Noriyuki Miura; Makoto Nagata (IEICE Trans. Electron., 2019)

Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices. - Takuji Miki; Makoto Nagata; Hiroki Sonoda; Noriyuki Miura; Takaaki Okidono; Yuuki Araga; Naoya Watanabe; Haruo Shimamoto; Katsuya Kikuchi (IEEE J. Solid State Circuits, 2020)

A Random Interrupt Dithering SAR Technique for Secure ADC Against Reference-Charge Side-Channel Attack. - Takuji Miki; Noriyuki Miura; Hiroki Sonoda; Kento Mizuta; Makoto Nagata (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

Voltage Surges by Backside ESD Impacts on IC Chip in Flip Chip Packaging. - Takuya Wadatsumi; Kohei Kawai; Rikuu Hasegawa; Takuji Miki; Makoto Nagata; Kikuo Muramatsu; Hiromu Hasegawa; Takuya Sawada; Takahito Fukushima; Hisashi Kondo (IRPS, 2022)

Testing Embedded Toggle Generation Through On-Chip IR-Drop Measurements. - Kazuki Monta; Leonidas Katselas; Ferenc Fodor; Takuji Miki; Alkis A. Hatzopoulos; Makoto Nagata; Erik Jan Marinissen (IEEE Des. Test, 2022)

An 11-bit 0.008mm2 charge-redistribution digital-to-analog converter operating at cryogenic temperature for large-scale qubit arrays. - Takuji Miki; Ryozo Takahashi; Makoto Nagata (IEICE Electron. Express, 2022)

Physical Attack Protection Techniques for IC Chip Level Hardware Security. - Makoto Nagata; Takuji Miki; Noriyuki Miura (IEEE Trans. Very Large Scale Integr. Syst., 2022)

A 13-bit Radiation-Hardened SAR-ADC with Error Correction by Adaptive Topology Transformation. - Yuya Aoki; Tatsuya Iwata; Takuji Miki; Kazutoshi Kobayashi; Takefumi Yoshikawa (IRPS, 2023)

Characterization of Backside ESD Impacts on Integrated Circuits. - Takuya Wadatsumi; Kohei Kawai; Rikuu Hasegawa; Kazuki Monta; Takuji Miki; Makoto Nagata (IRPS, 2023)

A Triturated Sensing System. - Noriyuki Miura; Kotaro Naruse; Jun Shiomi; Yoshihiro Midoh; Tetsuya Hirose; Takaaki Okidono; Takuji Miki; Makoto Nagata (ISSCC, 2023)

An Analog Side-Channel Attack on a High-Speed Asynchronous SAR ADC Using Dual Neural Network Technique. - Ryozo Takahashi; Takuji Miki; Makoto Nagata (IEICE Trans. Electron., 2023)

Experimental Exploration of the Backside ESD Impacts on an IC Chip in Flip Chip Packaging. - Takuya Wadatsumi; Kohei Kawai; Rikuu Hasegawa; Kikuo Muramatsu; Hiromu Hasegawa; Takuya Sawada; Takahito Fukushima; Hisashi Kondo; Takuji Miki; Makoto Nagata (IEICE Trans. Electron., 2023)

Thermal Flow Simuation and Measurements of 3D Si Chip Stacks with TSVs. - Shuhei Yokota; Rikuu Hasegawa; Kazuki Monta; Takaaki Okidono; Takuji Miki; Makoto Nagata (3DIC, 2024)

A Hybrid Simulation Approach for Accurate and Fast System-Level Side-Channel Leakage Evaluation. - Kazuki Monta; Takafumi Oki; Rikuu Hasegawa; Takuya Wadatsumi; Takuji Miki; Makoto Nagata; Lang Lin; Norman Chang (AsianHOST, 2024)

A cryogenic pulse shaper for spin qubit control utilizing 1ns-time-resolution ADCs on an active silicon interposer operating at sub-100 mK temperatures. - Ryozo Takahashi; Yusuke Kanno; Takuji Miki; Nobuhiro Kusuno; Hiroyuki Mizuno; Makoto Nagata (A-SSCC, 2024)

On-Chip Evaluation of Voltage Drops and Fault Occurrence Induced by Si Backside EM Injection. - Rikuu Hasegawa; Kazuki Monta; Takuya Wadatsumi; Takuji Miki; Makoto Nagata (COSADE, 2024)

Modeling and Analysis of On-Chip Voltage Fluctuations Caused by Electromagnetic Fault Injection. - Takuya Wadatsumi; Rikuu Hasegawa; Kazuki Monta; Takuji Miki; Lang Lin; Norman Chang; Makoto Nagata (EMC Compo, 2024)

Fault Injection Attacks Exploiting High Voltage Pulsing over Si-Substrate Backside of IC chips. - Yusuke Hayashi; Rikuu Hasegawa; Takuya Wadatsumi; Kazuki Monta; Takuji Miki; Makoto Nagata (FDTC, 2024)

Si-Backside Side-Channel Leakage Measurement and Simulation. - Rikuu Hasegawa; Kazuki Monta; Takuya Wadatsumi; Takuji Miki; Makoto Nagata; Lang Lin; Akhilesh Kumar; Norman Chang (ISOCC, 2024)

Cryo-CMOS Analog Circuits for Spin Qubit Control. - Takuji Miki (ASP-DAC, 2025)