A 10-Gb/s CMOS clock and data recovery circuit with an analog phase interpolator. - Rainer Kreienkamp; Ulrich Langmann; Christoph Zimmermann; Takuma Aoyama (CICC, 2003)

A 10-gb/s CMOS clock and data recovery circuit with an analog phase interpolator. - Rainer Kreienkamp; Ulrich Langmann; Christoph Zimmermann; Takuma Aoyama; Hubert Siedhoff (IEEE J. Solid State Circuits, 2005)

A 464GOPS 620GOPS/W heterogeneous multi-core SoC for image-recognition applications. - Yasuki Tanabe; Masato Sumiyoshi; Manabu Nishiyama; Itaru Yamazaki; Shinsuke Fujii; Katsuyuki Kimura; Takuma Aoyama; Moriyasu Banno; Hiroo Hayashi; Takashi Miyamori (ISSCC, 2012)

A UHS-II SD card controller with 240MB/s write throughput and 260MB/s read throughput. - Kenta Yasufuku; Naoto Oshiyama; Toshitada Saito; Yukimasa Miyamoto; Yutaka Nakamura; Ryota Terauchi; Atsushi Kondo; Takuma Aoyama; Masafumi Takahashi; Yukihito Oowaki; Ryoichi Bandai (A-SSCC, 2014)

19.3 66.3KIOPS-random-read 690MB/s-sequential-read universal Flash storage device controller with unified memory extension. - Konosuke Watanabe; Kenichiro Yoshii; Nobuhiro Kondo; Ken-ichi Maeda; Toshio Fujisawa; Junji Wadatsumi; Daisuke Miyashita; Shouhei Kousai; Yasuo Unekawa; Shinsuke Fujii; Takuma Aoyama; Takayuki Tamura; et al. (ISSCC, 2014)

A 6.4Gbps/pin NAND Flash Memory Multi-Chip Package Employing a Frequency Multiplying Bridge Chip for Scalable Performance and Capacity Storage Systems. - Shinichi Ikeda; Akira Iwata; Goichi Otomo; Tomoaki Suzuki; Hiroaki Iijima; Mikio Shiraishi; Shinya Kawakami; Masatomo Eimitsu; Yoshiki Matsuoka; Kiyohito Sato; Shigehiro Tsuchiya; Yoshinori Shigeta; et al. (A-SSCC, 2023)