Evaluation of on-chip transmission line interconnect using wire length distribution. - Junpei Inoue; Hiroyuki Ito; Shinichiro Gomi; Takanori Kyogoku; Takumi Uezono; Kenichi Okada 001; Kazuya Masu (ASP-DAC, 2005)

Wire Length Distribution Model Considering Core Utilization for System on Chip. - Takanori Kyogoku; Junpei Inoue; Hidenari Nakashima; Takumi Uezono; Kenichi Okada 001; Kazuya Masu (ISVLSI, 2005)

Prediction of delay time for future LSI using on-chip transmission line interconnects. - Takumi Uezono; Junpei Inoue; Takanori Kyogoku; Kenichi Okada 001; Kazuya Masu (SLIP, 2005)

Wire Length Distribution Model for System LSI. - Takanori Kyogoku; Junpei Inoue; Hidenari Nakashima; Takumi Uezono; Kenichi Okada 001; Kazuya Masu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

Via Distribution Model for Yield Estimation. - Takumi Uezono; Kenichi Okada 001; Kazuya Masu (ISQED, 2006)

Estimation of Power Reduction by On-Chip Transmission Line for 45nm Technology. - Kenichi Okada 001; Takumi Uezono; Kazuya Masu (PATMOS, 2006)

Statistical Modeling of a Via Distribution for Yield Estimation. - Takumi Uezono; Kenichi Okada 001; Kazuya Masu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

Improvement of power distribution network using correlation-based regression analysis. - Shiho Hagiwara; Takumi Uezono; Takashi Sato 001; Kazuya Masu (ACM Great Lakes Symposium on VLSI, 2007)

A MOS Transistor-Array for Accurate Measurement of Subthreshold Leakage Variation. - Takashi Sato 001; Takumi Uezono; Shiho Hagiwara; Kenichi Okada 001; Shuhei Amakawa; Noriaki Nakayama; Kazuya Masu (ISQED, 2007)

Weakness Identification for Effective Repair of Power Distribution Network. - Takashi Sato 001; Shiho Hagiwara; Takumi Uezono; Kazuya Masu (PATMOS, 2007)

Adaptable wire-length distribution with tunable occupation probability. - Shuhei Amakawa; Takumi Uezono; Takashi Sato 001; Kenichi Okada 001; Kazuya Masu (SLIP, 2007)

Application of Correlation-Based Regression Analysis for Improvement of Power Distribution Network. - Shiho Hagiwara; Takumi Uezono; Takashi Sato 001; Kazuya Masu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

An Adaptive Test for Parametric Faults Based on Statistical Timing Information. - Michihiro Shintani; Takumi Uezono; Tomoyuki Takahashi; Hiroyuki Ueyama; Takashi Sato 001; Kazumi Hatayama; Takashi Aikyo; Kazuya Masu (Asian Test Symposium, 2009)

One-Shot Voltage-Measurement Circuit Utilizing Process Variation. - Takumi Uezono; Takashi Sato 001; Kazuya Masu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Decomposition of drain-current variation into gain-factor and threshold voltage variations. - Takashi Sato 001; Takumi Uezono; Noriaki Nakayama; Kazuya Masu (ISCAS, 2010)

Scan based process parameter estimation through path-delay inequalities. - Takumi Uezono; Tomoyuki Takahashi; Michihiro Shintani; Kazumi Hatayama; Kazuya Masu; Hiroyuki Ochi; Takashi Sato 001 (ISCAS, 2010)

Path clustering for adaptive test. - Takumi Uezono; Tomoyuki Takahashi; Michihiro Shintani; Kazumi Hatayama; Kazuya Masu; Hiroyuki Ochi; Takashi Sato 001 (VTS, 2010)

A Time-Slicing Ring Oscillator for Capturing Time-Dependent Delay Degradation and Power Supply Voltage Fluctuation. - Takumi Uezono; Kazuya Masu; Takashi Sato 001 (IEICE Trans. Electron., 2010)

A Variability-Aware Adaptive Test Flow for Test Quality Improvement. - Michihiro Shintani; Takumi Uezono; Tomoyuki Takahashi; Kazumi Hatayama; Takashi Aikyo; Kazuya Masu; Takashi Sato 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Evaluation Technique for Soft-Error Rate in Terrestrial Environment Utilizing Low-Energy Neutron Irradiation. - Takumi Uezono; Tadanobu Toba; Ken-ichi Shimbo; Fumihiko Nagasaki; Kenji Kawamura (ATS, 2016)

Path Clustering for Test Pattern Reduction of Variation-Aware Adaptive Path Delay Testing. - Michihiro Shintani; Takumi Uezono; Kazumi Hatayama; Kazuya Masu; Takashi Sato 001 (J. Electron. Test., 2016)

Concurrent Detection of Failures in GPU Control Logic for Reliable Parallel Computing. - Hiroaki Itsuji; Takumi Uezono; Tadanobu Toba; Kojiro Ito; Masanori Hashimoto (ITC, 2020)

Efficient Functional In-Field Self-Test for Deep Learning Accelerators. - Yi He 010; Takumi Uezono; Yanjing Li (ITC, 2021)

Estimating Vulnerability of All Model Parameters in DNN with a Small Number of Fault Injections. - Yangchao Zhang; Hiroaki Itsuji; Takumi Uezono; Tadanobu Toba; Masanori Hashimoto (DATE, 2022)

Achieving Automotive Safety Requirements through Functional In-Field Self-Test for Deep Learning Accelerators. - Takumi Uezono; Yi He 010; Yanjing Li (ITC, 2022)

An Intelligent Diagnostic Technique for Reliable Operation of Edge AI. - Hiroaki Itsuji; Takumi Uezono; Tadanobu Toba; Subrata Kumar Kundu (ITSC, 2023)

Vulnerability Estimation of DNN Model Parameters with Few Fault Injections. - Yangchao Zhang; Hiroaki Itsuji; Takumi Uezono; Tadanobu Toba; Masanori Hashimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2023)

Hardware Error Detection with In-Situ Monitoring of Control Flow-Related Specifications. - Tomonari Tanaka; Takumi Uezono; Kohei Suenaga; Masanori Hashimoto (ASP-DAC, 2025)

A Hardware-Aware Failure-Detection Method for GPU Control-Logic. - Hiroaki Itsuji; Takumi Uezono; Tadanobu Toba; Kojiro Ito; Masanori Hashimoto (IEEE Access, 2025)

In-Situ Hardware Error Detection Using Specification-Derived Petri Net Models and Behavior-Derived State Sequences. - Tomonari Tanaka; Takumi Uezono; Kohei Suenaga; Masanori Hashimoto (CoRR, 2025)