A Context Dependent Clock Control Mechanism for Dynamically Reconfigurable Processors. - Hideharu Amano; Yohei Hasegawa; Shohei Abe; Kenichiro Ishikawa; Shunsuke Tsutsumi; Shunsuke Kurotaki; Takuro Nakamura; Takashi Nishimura (FPL, 2006)

Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor. - Yohei Hasegawa; Shohei Abe; Shunsuke Kurotaki; Vu Manh Tuan; Naohiro Katsura; Takuro Nakamura; Takashi Nishimura; Hideharu Amano (IPDPS, 2006)

Overwrite Configuration Technique in Multicast Configuration Scheme for Dynamically Reconfigurable Processor Arrays. - Satoshi Tsutsumi; Vasutan Tunbunheng; Yohei Hasegawa; Adepu Parimala; Takuro Nakamura; Takashi Nishimura; Hideharu Amano (FPT, 2007)

Power reduction techniques for Dynamically Reconfigurable Processor Arrays. - Takashi Nishimura; Keiichiro Hirai; Yoshiki Saito; Takuro Nakamura; Yohei Hasegawa; Satoshi Tsutsumi; Vasutan Tunbunheng; Hideharu Amano (FPL, 2008)

Exploring the optimal size for multicasting configuration data of dynamically reconfigurable processors. - Takuro Nakamura; Toru Sano; Yohei Hasegawa; Satoshi Tsutsumi; Vasutan Tunbunheng; Hideharu Amano (FPT, 2008)

Leakage power reduction for coarse grained dynamically reconfigurable processor arrays with fine grained Power Gating technique. - Yoshiki Saito; Tomoaki Shirai; Takuro Nakamura; Takashi Nishimura; Yohei Hasegawa; Satoshi Tsutsumi; Toshihiro Kashima; Mitsutaka Nakata; Seidai Takeda; Kimiyoshi Usami; Hideharu Amano (FPT, 2008)