A 19nm 112.8mm2 64Gb multi-level flash memory with 400Mb/s/pin 1.8V Toggle Mode interface. - Noboru Shibata; Kazushige Kanda; Toshiki Hisada; Katsuaki Isobe; Manabu Sato; Yui Shimizu; Takahiro Shimizu; Takahiro Sugimoto; Tomohiro Kobayashi; Kazuko Inuzuka; Naoaki Kanagawa; Yasuyuki Kajitani; et al. (ISSCC, 2012)

11.1 A 512Gb 3b/cell flash memory on 64-word-line-layer BiCS technology. - Ryuji Yamashita; Sagar Magia; Tsutomu Higuchi; Kazuhide Yoneya; Toshio Yamamura; Hiroyuki Mizukoshi; Shingo Zaitsu; Minoru Yamashita; Shunichi Toyama; Norihiro Kamae; Juan Lee; Shuo Chen; et al. (ISSCC, 2017)

A 512Gb 3-bit/Cell 3D Flash Memory on 128-Wordline-Layer with 132MB/s Write Performance Featuring Circuit-Under-Array Technology. - Chang Hua Siau; Kwang-Ho Kim; Seungpil Lee; Katsuaki Isobe; Noboru Shibata; Kapil Verma; Takuya Ariki; Jason Li 001; Jong Yuh; Anirudh Amarnath; Qui Nguyen; Ohwon Kwon; et al. (ISSCC, 2019)

Crossed Bit Line (CBL) Architecture in 3D Flash Memory CMOS Directly Bonded to Array (CBA) Structure. - Hiroshi Maejima; Katsuaki Isobe; N. Okada; Masaki Unno; T. Hashimoto; Tetsuaki Utsumi; T. Hisada; K. Maruyama; Toshiyuki Kouchi; T. Kotani; Hitoshi Shiga; O. Kwon; et al. (IMW, 2025)

A 1Tb 3b/cell 3D-Flash Memory with a 29%-Improved-Energy-Efficiency Read Operation and 4.8Gb/s Power-Isolated Low-Tapped-Termination I/Os. - Kosuke Yanagidaira; Mario Sako; Yasuhiro Hirashima; Junya Matsuno; Yumi Higashi; Yutaka Shimizu; Akihiro Imamoto; Kazuaki Kawaguchi; Koji Tabata; Takeshi Nakano; Yusuke Ochi; Hiroaki Hoshino; et al. (ISSCC, 2025)