IMAP-CE: a 51.2 GOPS video rate image processor with 128 VLIW processing elements. - Shorin Kyo; Takuya Koga; Shin'ichiro Okazaki (ICIP (3), 2001)

A 51.2-GOPS scalable video recognition processor for intelligent cruise control based on a linear array of 128 four-way VLIW processing elements. - Shorin Kyo; Takuya Koga; Shin'ichiro Okazaki; Ichiro Kuroda (IEEE J. Solid State Circuits, 2003)

A 51.2 GOPS Programmable Video Recognition Processor for Vision-Based Intelligent Cruise Control Applications. - Shorin Kyo; Takuya Koga; Shin'ichiro Okazaki; Ichiro Kuroda (IEICE Trans. Inf. Syst., 2004)

A low-cost mixed-mode parallel processor architecture for embedded systems. - Shorin Kyo; Takuya Koga; Hanno Lieske; Shouhei Nomoto; Shin'ichiro Okazaki (ICS, 2007)

IMAPCAR2: A dynamic SIMD/MIMD mode switching processor for embedded systems. - Shorin Kyo; Shouhei Nomoto; Takuya Koga; Hanno Lieske; Shin'ichiro Okazaki (Hot Chips Symposium, 2009)