Improving instruction level parallelism through reconfigurable units in superscalar processors. - Tameesh Suri (SIGARCH Comput. Archit. News, 2007)

Scalable Multi-cores with Improved Per-core Performance Using Off-the-critical Path Reconfigurable Hardware. - Tameesh Suri; Aneesh Aggarwal (HiPC, 2008)

Improving performance of simple cores by exploiting loop-level parallelism through value prediction and reconfiguration. - Tameesh Suri; Aneesh Aggarwal (Conf. Computing Frontiers, 2009)

Improving Scalability and Per-Core Performance in Multi-Cores through Resource Sharing and Reconfiguration. - Tameesh Suri; Aneesh Aggarwal (VLSI Design, 2009)

Improving Adaptability and Per-Core Performance of Many-Core Processors Through Reconfiguration. - Tameesh Suri; Aneesh Aggarwal (Int. J. Parallel Program., 2010)

SIFT: a low-overhead dynamic information flow tracking architecture for SMT processors. - Meltem Ozsoy; Dmitry Ponomarev 001; Nael B. Abu-Ghazaleh; Tameesh Suri (Conf. Computing Frontiers, 2011)

SIFT: Low-Complexity Energy-Efficient Information Flow Tracking on SMT Processors. - Meltem Ozsoy; Dmitry Ponomarev 001; Nael B. Abu-Ghazaleh; Tameesh Suri (IEEE Trans. Computers, 2014)

Performance Characterization of Hyperscale Applicationson on NVMe SSDs. - Qiumin Xu; Huzefa Siyamwala; Mrinmoy Ghosh; Manu Awasthi; Tameesh Suri; Zvika Guz; Anahita Shayesteh; Vijay Balakrishnan (SIGMETRICS, 2015)

Performance analysis of NVMe SSDs and their implication on real world databases. - Qiumin Xu; Huzefa Siyamwala; Mrinmoy Ghosh; Tameesh Suri; Manu Awasthi; Zvika Guz; Anahita Shayesteh; Vijay Balakrishnan (SYSTOR, 2015)

System-Level Characterization of Datacenter Applications. - Manu Awasthi; Tameesh Suri; Zvika Guz; Anahita Shayesteh; Mrinmoy Ghosh; Vijay Balakrishnan (ICPE, 2015)

Adaptive and Scalable Predictive Page Policies for High Core-Count Server CPUs. - Tameesh Suri; Aneesh Aggarwal (ARCS, 2017)