Clocking Links in Multi-chip Packages: A Case Study. - Tamer A. Ali 001; Dinesh Patil; Frankie Liu; Elad Alon; Jon K. Lexau; Chih-Kong Ken Yang; Ron Ho (Hot Interconnects, 2010)

A 4.6GHz MDLL with -46dBc reference spur and aperture position tuning. - Tamer A. Ali 001; Amr Amin Hafez; Robert J. Drost; Ronald Ho; Chih-Kong Ken Yang (ISSCC, 2011)

A dual 23Gb/s CMOS transmitter/receiver chipset for 40Gb/s RZ-DQPSK and CS-RZ-DQPSK optical transmission. - Delong Cui; Bharath Raghavan; Ullas Singh; Anand Vasani; Zhi Chao Huang; Deyi Pi; Mehdi Khanpour; Ali Nazemi; Hassan Maarefi; Tamer A. Ali 001; Nick Huang; Wei Zhang; et al. (ISSCC, 2012)

A 100+ meter 12Gb/s/lane copper cable link based on clock-forwarding. - Tamer A. Ali 001; Won Ho Park; Preeti Mulage; E-Hung Chen; Ron Ho; Chih-Kong Ken Yang (VLSIC, 2012)

A Dual-Channel 23-Gbps CMOS Transmitter/Receiver Chipset for 40-Gbps RZ-DQPSK and CS-RZ-DQPSK Optical Transmission. - Delong Cui; Bharath Raghavan; Ullas Singh; Anand Vasani; Zhi Chao Huang; Deyi Pi; Mehdi Khanpour; Ali Nazemi; Hassan Maarefi; Wei Zhang; Tamer A. Ali 001; Nick Huang; et al. (IEEE J. Solid State Circuits, 2012)

Design of a 100+ meter 12Gb/s/Lane Copper Cable Link Based on Clock-Forwarding. - Tamer A. Ali 001 (2012)

A Sub-200 fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications. - Burak Çatli; Ali Nazemi; Tamer A. Ali 001; Siavash Fallahi; Yang Liu; Jaehyup Kim; Mohammed M. Abdul-Latif; Mahmoud Reza Ahmadi; Hassan Maarefi; Afshin Momtaz; Namik Kocaman (CICC, 2013)

A 100+ Meter 12 Gb/s/Lane Copper Cable Link Based on Clock-Forwarding. - Tamer A. Ali 001; Robert J. Drost; Ron Ho; Chih-Kong Ken Yang (IEEE J. Solid State Circuits, 2013)

A 23mW/lane 1.2-6.8Gb/s multi-standard transceiver in 28nm CMOS. - Seong-Ho Lee; Duke Tran; Tamer A. Ali 001; Burak Çatli; Heng Zhang; Wei Zhang; Mohammed M. Abdul-Latif; Zhi Huang; Guansheng Li; Mahmoud Reza Ahmadi; Afshin Momtaz (A-SSCC, 2014)

A 3.8 mW/Gbps Quad-Channel 8.5-13 Gbps Serial Link With a 5 Tap DFE and a 4 Tap Transmit FFE in 28 nm CMOS. - Namik Kocaman; Tamer A. Ali 001; Lakshmi P. Rao; Ullas Singh; Mohammed M. Abdul-Latif; Yang Liu; Amr Amin Hafez; Henry Park; Anand Vasani; Zhi Huang; Arvindh Iyer; Bo Zhang 029; et al. (IEEE J. Solid State Circuits, 2016)

29.2 A transmitter and receiver for 100Gb/s coherent networks with integrated 4×64GS/s 8b ADCs and DACs in 20nm CMOS. - Jun Cao 001; Delong Cui; Ali Nazemi; Tim He; Guansheng Li; Burak Çatli; Mehdi Khanpour; Kangmin Hu; Tamer A. Ali 001; Heng Zhang; Hairong Yu; Ben Rhew; et al. (ISSCC, 2017)

A 180mW 56Gb/s DSP-Based Transceiver for High Density IOs in Data Center Switches in 7nm FinFET Technology. - Tamer A. Ali 001; Ramy Yousry; Henry Park; Ehung Chen; Po-Shuan Weng; Yi-Chieh Huang; Chun-Cheng Liu; Chien-Hua Wu; Shih-Hao Huang; Chungshi Lin; Ke-Chung Wu; Kun-Hung Tsai; et al. (ISSCC, 2019)

6.2 A 460mW 112Gb/s DSP-Based Transceiver with 38dB Loss Compensation for Next-Generation Data Centers in 7nm FinFET Technology. - Tamer A. Ali 001; Ehung Chen; Henry Park; Ramy Yousry; Yu-Ming Ying; Mohammed Abdullatif; Miguel Gandara; Chun-Cheng Liu; Po-Shuan Weng; Huan-Sheng Chen; Mohammad Elbadry; Qaiser Nehal; et al. (ISSCC, 2020)

56/112Gbps Wireline Transceivers for Next Generation Data Centers on 7nm FINFET CMOS Technology. - Tamer A. Ali 001; Mohammed Abdullatif; Henry Park; Ehung Chen; Ramy Awad; Miguel Gandara (CICC, 2021)

11.1 A 1.7pJ/b 112Gb/s XSR Transceiver for Intra-Package Communication in 7nm FinFET Technology. - Ramy Yousry; Ehung Chen; Yu-Ming Ying; Mohammed Abdullatif; Mohammad Elbadry; Ahmed ElShater; Tsz-Bin Liu; Joonyeong Lee; Dhinessh Ramachandran; Kaiz Wang; Chih-Hao Weng; Mau-Lin Wu; et al. (ISSCC, 2021)

A 4.63pJ/b 112Gb/s DSP-Based PAM-4 Transceiver for a Large-Scale Switch in 5nm FinFET. - Henry Park; Mohammed Abdullatif; Ehung Chen; Ahmed Elmallah; Qaiser Nehal; Miguel Gandara; Tsz-Bin Liu; Amr Khashaba; Joonyeong Lee; Chih-Yi Kuan; Dhinessh Ramachandran; Ruey-Bo Sun; et al. (ISSCC, 2023)

18.1 A 600Gb/s DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GS/s 8b ADC/DAC in 16nm CMOS. - Guansheng Li; Adesh Garg; Tim He; Ullas Singh; Jiawen Zhang; Lakshmi P. Rao; Chang Liu; Meisam Honarvar Nazari; Yang Liu; Yong Liu; Heng Zhang; Tamer A. Ali 001; et al. (ISSCC, 2024)

7.1 A 212.5Gb/s DSP-Based PAM-4 Transceiver with 50dB Loss Compensation for Large AI System Interconnects in 4nm FinFET. - Ehung Chen; Henry Park; Mohammed Abdullatif; Miguel Gandara; Ahmed ElShater; Amr Khashaba; Shih-Hao Huang; Tsz-Bin Liu; Atharav Atharav; Joonyeong Lee; Qaiser Nehal; Mohamed Megahed; et al. (ISSCC, 2025)