An Algorithm for Locating Logic Design Errors. - Masahiro Tomita; Hong-Hai Jiang; Tamotsu Yamamoto; Yoshihiro Hayashi (ICCAD, 1990)

Rectification of Multiple Logic Design Errors in Multiple Output Circuits. - Masahiro Tomita; Tamotsu Yamamoto; Fuminori Sumikawa; Kotaro Hirano (DAC, 1994)