Estimation of circuit activity considering signal correlations and simultaneous switching. - Tan-Li Chou; Kaushik Roy 001; Sharat Prasad (ICCAD, 1994)

Statistical estimation of sequential circuit activity. - Tan-Li Chou; Kaushik Roy 001 (ICCAD, 1995)

Estimation of sequential circuit activity considering spatial and temporal correlations. - Tan-Li Chou; Kaushik Roy 001 (ICCD, 1995)

Estimation of activity for static and domino CMOS circuits considering signal correlations and simultaneous switching. - Tan-Li Chou; Kaushik Roy 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

Accurate power estimation of CMOS sequential circuits. - Tan-Li Chou; Kaushik Roy 001 (IEEE Trans. Very Large Scale Integr. Syst., 1996)

Power sensitivity - a new method to estimate power dissipation considering uncertain specifications of primary inputs. - Zhanping Chen; Kaushik Roy 001; Tan-Li Chou (ICCAD, 1997)

Low-Power Driven Logic Synthesis Using Accurate Power Estimation Technique. - Priya Patil; Tan-Li Chou; Kaushik Roy 001; Rabindra Roy (VLSI Design, 1997)

Power Estimation Under Uncertain Delays. - Tan-Li Chou; Kaushik Roy 001 (Integr. Comput. Aided Eng., 1998)

Efficient statistical approach to estimate power considering uncertain properties of primary inputs. - Zhanping Chen; Kaushik Roy 001; Tan-Li Chou (IEEE Trans. Very Large Scale Integr. Syst., 1998)

Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion. - I-Min Liu; Tan-Li Chou; Adnan Aziz; D. F. Wong 001 (ISPD, 2000)

Estimating Circuit Activity in Combinational CMOS Digital Circuits. - Hendrawan Soeleman; Kaushik Roy 001; Tan-Li Chou (IEEE Des. Test Comput., 2000)

Integrated power supply planning and floorplanning. - I-Min Liu; Hung-Ming Chen; Tan-Li Chou; Adnan Aziz; D. F. Wong 001 (ASP-DAC, 2001)

An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications. - Yu-Der Chih; Po-Hao Lee; Hidehiro Fujiwara; Yi-Chun Shih; Chia-Fu Lee; Rawan Naous; Yu-Lin Chen; Chieh-Pu Lo; Cheng-Han Lu; Haruki Mori; Wei-Cheng Zhao; Dar Sun; et al. (ISSCC, 2021)

A 5-nm 254-TOPS/W 221-TOPS/mm2 Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations. - Hidehiro Fujiwara; Haruki Mori; Wei-Chang Zhao; Mei-Chen Chuang; Rawan Naous; Chao-Kai Chuang; Takeshi Hashizume; Dar Sun; Chia-Fu Lee; Kerem Akarvardar; Saman Adham; Tan-Li Chou; et al. (ISSCC, 2022)

A 12nm 121-TOPS/W 41.6-TOPS/mm2 All Digital Full Precision SRAM-based Compute-in-Memory with Configurable Bit-width For AI Edge Applications. - Chia-Fu Lee; Cheng-Han Lu; Cheng-En Lee; Haruki Mori; Hidehiro Fujiwara; Yi-Chun Shih; Tan-Li Chou; Yu-Der Chih; Tsung-Yung Jonathan Chang (VLSI Technology and Circuits, 2022)

A 16nm 32Mb Embedded STT-MRAM with a 6ns Read-Access Time, a 1M-Cycle Write Endurance, 20-Year Retention at 150°C and MTJ-OTP Solutions for Magnetic Immunity. - Po-Hao Lee; Chia-Fu Lee; Yi-Chun Shih; Hon-Jarn Lin; Yen-An Chang; Cheng-Han Lu; Yu-Lin Chen; Chieh-Pu Lo; Chung-Chieh Chen; Cheng-Hsiung Kuo; Tan-Li Chou; Chia-Yu Wang; et al. (ISSCC, 2023)

A 4nm 6163-TOPS/W/b $ mathbf{4790-TOPS/mm^{2}/b}$ SRAM Based Digital-Computing-in-Memory Macro Supporting Bit-Width Flexibility and Simultaneous MAC and Weight Update. - Haruki Mori; Wei-Chang Zhao; Cheng-En Lee; Chia-Fu Lee; Yu-Hao Hsu; Chao-Kai Chuang; Takeshi Hashizume; Hao-Chun Tung; Yao-Yi Liu; Shin-Rung Wu; Kerem Akarvardar; Tan-Li Chou; et al. (ISSCC, 2023)

34.4 A 3nm, 32.5TOPS/W, 55.0TOPS/mm2 and 3.78Mb/mm2 Fully-Digital Compute-in-Memory Macro Supporting INT12 × INT12 with a Parallel-MAC Architecture and Foundry 6T-SRAM Bit Cell. - Hidehiro Fujiwara; Haruki Mori; Wei-Chang Zhao; Kinshuk Khare; Cheng-En Lee; Xiaochen Peng; Vineet Joshi; Chao-Kai Chuang; Shu-Huan Hsu; Takeshi Hashizume; Toshiaki Naganuma; Chen-Hung Tien; et al. (ISSCC, 2024)