Structural and behavioral synthesis for testability techniques. - Chung-Hsing Chen; Tanay Karnik; Daniel G. Saab (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

An empirical model for accurate estimation of routing delay in FPGAs. - Tanay Karnik; Sung-Mo Kang (ICCAD, 1995)

Microprocessor Layout Method. - Tanay Karnik (The VLSI Handbook, 1999)

Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors. - Tanay Karnik; Yibin Ye; James W. Tschanz; Liqiong Wei; Steven M. Burns; Venkatesh Govindarajulu; Vivek De; Shekhar Borkar (DAC, 2002)

Sub-90nm technologies: challenges and opportunities for CAD. - Tanay Karnik; Shekhar Borkar; Vivek De (ICCAD, 2002)

Parameter variations and impact on circuits and microarchitecture. - Shekhar Borkar; Tanay Karnik; Siva G. Narendra; James W. Tschanz; Ali Keshavarzi; Vivek De (DAC, 2003)

Design and reliability challenges in nanometer technologies. - Shekhar Borkar; Tanay Karnik; Vivek De (DAC, 2004)

HiSIM: hierarchical interconnect-centric circuit simulator. - Tsung-Hao Chen; Jeng-Liang Tsai; Tanay Karnik (ICCAD, 2004)

Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation. - Gerhard Schrom; Peter Hazucha; Jae-Hong Hahn; Volkan Kursun; Donald S. Gardner; Siva G. Narendra; Tanay Karnik; Vivek De (ISLPED, 2004)

Measurements and analysis of SER-tolerant latch in a 90-nm dual-VT CMOS process. - Peter Hazucha; Tanay Karnik; Steven Walstra; Bradley A. Bloechel; James W. Tschanz; Jose Maiz; Krishnamurthy Soumyanath; Gregory E. Dermer; Siva G. Narendra; Vivek De; Shekhar Borkar (IEEE J. Solid State Circuits, 2004)

Characterization of Soft Errors Caused by Single Event Upsets in CMOS Processes. - Tanay Karnik; Peter Hazucha; Jagdish Patel (IEEE Trans. Dependable Secur. Comput., 2004)

Logic soft errors in sub-65nm technologies design and CAD challenges. - Subhasish Mitra; Tanay Karnik; Norbert Seifert; Ming Zhang (DAC, 2005)

Design of sub-90nm Circuits and Design Methodologies. - Anirudh Devgan; Ruchir Puri; Sachin Sapatnaker; Tanay Karnik; Rajiv V. Joshi (ISQED, 2005)

Area-efficient linear regulator with ultra-fast load regulation. - Peter Hazucha; Tanay Karnik; Bradley A. Bloechel; Colleen Parsons; David Finan; Shekhar Borkar (IEEE J. Solid State Circuits, 2005)

A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package. - Peter Hazucha; Gerhard Schrom; Jaehong Hahn; Bradley A. Bloechel; Paul Hack; Gregory E. Dermer; Siva G. Narendra; Donald S. Gardner; Tanay Karnik; Vivek De; Shekhar Borkar (IEEE J. Solid State Circuits, 2005)

High-frequency DC-DC conversion : fact or fiction. - Tanay Karnik; Peter Hazucha; Gerhard Schrom; Fabrice Paillet; Donald S. Gardner (ISCAS, 2006)

Power-efficient pulse width modulation DC/DC converters with zero voltage switching control. - Changbo Long; Sasank Reddy; Sudhakar Pamarti; Lei He 001; Tanay Karnik (ISLPED, 2006)

Thermal via allocation for 3D ICs considering temporally and spatially variant thermal power. - Hao Yu 001; Yiyu Shi 001; Lei He 001; Tanay Karnik (ISLPED, 2006)

A Linear Regulator with Fast Digital Control for Biasing Integrated DC-DC Converters. - Peter Hazucha; Sung Tae Moon; Gerhard Schrom; Fabrice Paillet; Donald S. Gardner; Saravanan Rajapandian; Tanay Karnik (ISSCC, 2006)

Technology Impacts on Sub-90nm CMOS Circuit Design and Design Methodologies. - Ruchir Puri; Tanay Karnik; Rajiv V. Joshi (VLSI Design, 2006)

High-voltage power delivery through charge recycling. - Saravanan Rajapandian; Kenneth L. Shepard; Peter Hazucha; Tanay Karnik (IEEE J. Solid State Circuits, 2006)

Low Voltage Buffered Bandgap Reference. - Peter Hazucha; Fabrice Paillet; Sung Tae Moon; David J. Rennie; Gerhard Schrom; Donald S. Gardner; Kenneth Ikeda; Gell Gellman; Tanay Karnik (ISQED, 2007)

Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging. - James W. Tschanz; Nam-Sung Kim; Saurabh Dighe; Jason Howard; Gregory Ruhl; Sriram R. Vangal; Siva G. Narendra; Yatin Hoskote; Howard Wilson; Carol Lam; Matthew Shuman; Carlos Tokunaga; et al. (ISSCC, 2007)

On-Die Supply-Resonance Suppression Using Band-Limited Active Damping. - Jianping Xu; Peter Hazucha; Mingwei Huang; Paolo A. Aseron; Fabrice Paillet; Gerhard Schrom; James W. Tschanz; Cangsang Zhao; Vivek De; Tanay Karnik; Greg Taylor (ISSCC, 2007)

High Voltage Tolerant Linear Regulator With Fast Digital Control for Biasing of Integrated DC-DC Converters. - Peter Hazucha; Sung Tae Moon; Gerhard Schrom; Fabrice Paillet; Donald S. Gardner; Saravanan Rajapandian; Tanay Karnik (IEEE J. Solid State Circuits, 2007)

Analytical Model for the Propagation Delay of Through Silicon Vias. - DiaaEldin Khalil; Yehea I. Ismail; Muhammad M. Khellah; Tanay Karnik; Vivek De (ISQED, 2008)

Energy-Efficient and Metastability-Immune Timing-Error Detection and Instruction-Replay-Based Recovery Circuits for Dynamic-Variation Tolerance. - Keith A. Bowman; James W. Tschanz; Nam-Sung Kim; Janice C. Lee; Chris Wilkerson; Shih-Lien Lu; Tanay Karnik; Vivek K. De (ISSCC, 2008)

2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process. - Dinesh Somasekhar; Yibin Ye; Paolo A. Aseron; Shih-Lien Lu; Muhammad M. Khellah; Jason Howard; Gregory Ruhl; Tanay Karnik; Shekhar Y. Borkar; Vivek De; Ali Keshavarzi (ISSCC, 2008)

A Band-Limited Active Damping Circuit With 13 dB Power Supply Resonance Reduction. - Jianping Xu; Peter Hazucha; Zuoguo Wu; Paolo A. Aseron; Mingwei Huang; Fabrice Paillet; Gerhard Schrom; James W. Tschanz; Vivek De; Tanay Karnik; Greg Taylor (IEEE J. Solid State Circuits, 2008)

Accurate Estimation of SRAM Dynamic Stability. - D. E. Khalil; Muhammad M. Khellah; Nam-Sung Kim; Yehea I. Ismail; Tanay Karnik; Vivek K. De (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Thermal Via Allocation for 3-D ICs Considering Temporally and Spatially Variant Thermal Power. - Hao Yu 001; Yiyu Shi 001; Lei He 001; Tanay Karnik (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Circuit techniques for dynamic variation tolerance. - Keith A. Bowman; James W. Tschanz; Chris Wilkerson; Shih-Lien Lu; Tanay Karnik; Vivek De; Shekhar Y. Borkar (DAC, 2009)

Resilient circuits - Enabling energy-efficient performance and reliability. - James W. Tschanz; Keith A. Bowman; Chris Wilkerson; Shih-Lien Lu; Tanay Karnik (ICCAD, 2009)

A Delay-Locked Loop Synchronization Scheme for High-Frequency Multiphase Hysteretic DC-DC Converters. - Pengfei Li 001; Lin Xue; Peter Hazucha; Tanay Karnik; Rizwan Bashirullah (IEEE J. Solid State Circuits, 2009)

Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance. - Keith A. Bowman; James W. Tschanz; Nam-Sung Kim; Janice C. Lee; Chris Wilkerson; Shih-Lien Lu; Tanay Karnik; Vivek K. De (IEEE J. Solid State Circuits, 2009)

Process, Temperature, and Supply-Noise Tolerant 45nm Dense Cache Arrays With Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits. - Muhammad M. Khellah; Nam-Sung Kim; Yibin Ye; Dinesh Somasekhar; Tanay Karnik; Nitin Borkar; Gunjan Pandya; Fatih Hamzaoglu; Tom Coan; Yih Wang; Kevin Zhang 001; Clair Webb; et al. (IEEE J. Solid State Circuits, 2009)

2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology. - Dinesh Somasekhar; Yibin Ye; Paolo A. Aseron; Shih-Lien Lu; Muhammad M. Khellah; Jason Howard; Gregory Ruhl; Tanay Karnik; Shekhar Borkar; Vivek K. De; Ali Keshavarzi (IEEE J. Solid State Circuits, 2009)

SRAM dynamic stability estimation using MPFP and its applications. - DiaaEldin Khalil; Muhammad M. Khellah; Nam-Sung Kim; Yehea I. Ismail; Tanay Karnik; Vivek De (Microelectron. J., 2009)

Resilient design in scaled CMOS for energy efficiency. - James W. Tschanz; Keith A. Bowman; Muhammad M. Khellah; Chris Wilkerson; Bibiche M. Geuskens; Dinesh Somasekhar; Arijit Raychowdhury; Jaydeep Kulkarni; Carlos Tokunaga; Shih-Lien Lu; Tanay Karnik; Vivek De (ASP-DAC, 2010)

Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency. - Keith A. Bowman; Carlos Tokunaga; James W. Tschanz; Arijit Raychowdhury; Muhammad M. Khellah; Bibiche M. Geuskens; Shih-Lien Lu; Paolo A. Aseron; Tanay Karnik; Vivek De (CICC, 2010)

Opportunities for PMOS read and write ports in low voltage dual-port 8T bit cell arrays. - Bibiche M. Geuskens; Muhammad M. Khellah; Jaydeep Kulkarni; Tanay Karnik; Vivek De (CICC, 2010)

Resilient microprocessor design for high performance & energy efficiency. - Keith A. Bowman; James W. Tschanz; Shih-Lien Lu; Paolo A. Aseron; Muhammad M. Khellah; Arijit Raychowdhury; Bibiche M. Geuskens; Carlos Tokunaga; Chris Wilkerson; Tanay Karnik; Vivek De (ISLPED, 2010)

PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction. - Arijit Raychowdhury; Bibiche M. Geuskens; Jaydeep Kulkarni; James W. Tschanz; Keith A. Bowman; Tanay Karnik; Shih-Lien Lu; Vivek De; Muhammad M. Khellah (ISSCC, 2010)

A 45nm resilient and adaptive microprocessor core for dynamic variation tolerance. - James W. Tschanz; Keith A. Bowman; Shih-Lien Lu; Paolo A. Aseron; Muhammad M. Khellah; Arijit Raychowdhury; Bibiche M. Geuskens; Carlos Tokunaga; Chris Wilkerson; Tanay Karnik; Vivek De (ISSCC, 2010)

Multi-Phase 1 GHz Voltage Doubler Charge Pump in 32 nm Logic Process. - Dinesh Somasekhar; Balaji Srinivasan; Gunjan Pandya; Fatih Hamzaoglu; Muhammad M. Khellah; Tanay Karnik; Kevin Zhang 001 (IEEE J. Solid State Circuits, 2010)

Coordinating 3D designs: Interface IP, standards or free form? - Paul D. Franzon; W. Rhett Davis; Zheng Zhou 004; Shivam Priyadarshi; Matthew Hogan; Tanay Karnik; Ganapti Srinavas (3DIC, 2011)

Integrated inductors with magnetic materials for on-chip power conversion. - Donald S. Gardner; Gerhard Schrom; Fabrice Paillet; Tanay Karnik; Shekhar Borkar (Hot Chips Symposium, 2011)

3DICs for tera-scale computing: a case study. - Tanay Karnik; Dinesh Somasekhar; Shekhar Borkar (ISPD, 2011)

Error Detection and Correction in Microprocessor Core and Memory Due to Fast Dynamic Voltage Droops. - Arijit Raychowdhury; Jim Tschanz; Keith A. Bowman; Shih-Lien Lu; Paolo A. Aseron; Muhammad M. Khellah; Bibiche M. Geuskens; Carlos Tokunaga; Chris Wilkerson; Tanay Karnik; Vivek De (IEEE J. Emerg. Sel. Topics Circuits Syst., 2011)

Microprocessor system applications and challenges for through-silicon-via-based three-dimensional integration. - Tanay Karnik; Dinesh Somasekhar; Shekhar Borkar (IET Comput. Digit. Tech., 2011)

A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance. - Keith A. Bowman; James W. Tschanz; Shih-Lien Lu; Paolo A. Aseron; Muhammad M. Khellah; Arijit Raychowdhury; Bibiche M. Geuskens; Carlos Tokunaga; Chris Wilkerson; Tanay Karnik; Vivek K. De (IEEE J. Solid State Circuits, 2011)

Tunable Replica Bits for Dynamic Variation Tolerance in 8T SRAM Arrays. - Arijit Raychowdhury; Bibiche M. Geuskens; Keith A. Bowman; James W. Tschanz; Shih-Lien Lu; Tanay Karnik; Muhammad M. Khellah; Vivek K. De (IEEE J. Solid State Circuits, 2011)

All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control. - Keith A. Bowman; Carlos Tokunaga; James W. Tschanz; Arijit Raychowdhury; Muhammad M. Khellah; Bibiche M. Geuskens; Shih-Lien Lu; Paolo A. Aseron; Tanay Karnik; Vivek K. De (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Design for test and reliability in ultimate CMOS. - Michael Nicolaidis; Lorena Anghel; Nacer-Eddine Zergainoh; Yervant Zorian; Tanay Karnik; Keith A. Bowman; James W. Tschanz; Shih-Lien Lu; Carlos Tokunaga; Arijit Raychowdhury; Muhammad M. Khellah; Jaydeep Kulkarni; et al. (DATE, 2012)

Scaling the "Memory Wall": Designer track. - Shih-Lien Lu; Tanay Karnik; Ganapati Srinivasa; Kai-Yuan Chao; Doug Carmean; Jim Held (ICCAD, 2012)

Capacitive-coupling wordline boosting with self-induced VCC collapse for write VMIN reduction in 22-nm 8T SRAM. - Jaydeep Kulkarni; Bibiche M. Geuskens; Tanay Karnik; Muhammad M. Khellah; James W. Tschanz; Vivek De (ISSCC, 2012)

A 22nm dynamically adaptive clock distribution for voltage droop tolerance. - Keith A. Bowman; Carlos Tokunaga; Tanay Karnik; Vivek K. De; Jim Tschanz (VLSIC, 2012)

Introduction to the Special Issue on the 2011 IEEE International Solid-State Circuits Conference. - Alice Wang; Ken Takeuchi; Tanay Karnik; Maysam Ghovanloo; Satoshi Shigematsu (IEEE J. Solid State Circuits, 2012)

Power management and delivery for high-performance microprocessors. - Tanay Karnik; Mondira (Mandy) Deb Pant; Shekhar Borkar (DAC, 2013)

F5: Frequency generation and clock distribution. - Antonio Liscidini; SeongHwan Cho; Tony Chan Carusone; Tanay Karnik; Mike Keaveney; Brian Otis; Aaron Partridge; Christoph Sandner (ISSCC, 2013)

Adaptive and Resilient Circuits for Dynamic Variation Tolerance. - Keith A. Bowman; Carlos Tokunaga; James W. Tschanz; Tanay Karnik; Vivek K. De (IEEE Des. Test, 2013)

A 22 nm All-Digital Dynamically Adaptive Clock Distribution for Supply Voltage Droop Tolerance. - Keith A. Bowman; Carlos Tokunaga; Tanay Karnik; Vivek K. De; James W. Tschanz (IEEE J. Solid State Circuits, 2013)

Resiliency for many-core system on a chip. - Tanay Karnik; James W. Tschanz; Nitin Borkar; Jason Howard; Sriram R. Vangal; Vivek De; Shekhar Borkar (ASP-DAC, 2014)

Application-Specific Cross-Layer Optimization Based on Predictive Variable-Latency VLSI Design. - Vivek K. De; Andrew B. Kahng; Tanay Karnik; Bao Liu 001; Milad Maleki; Lu Wang (ACM J. Emerg. Technol. Comput. Syst., 2015)

Editorial. - Krishnendu Chakrabarty; Massimo Alioto; Bevan M. Baas; Chirn Chye Boon; Meng-Fan Chang; Naehyuck Chang; Yao-Wen Chang; Chip-Hong Chang; Shih-Chieh Chang; Poki Chen; Masud H. Chowdhury; Pasquale Corsonello; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Closed yet open DRAM: achieving low latency and high performance in DRAM memory systems. - Lavanya Subramanian; Kaushik Vaidyanathan; Anant Nori; Sreenivas Subramoney; Tanay Karnik; Hong Wang 003 (DAC, 2018)

Technology trends, requirements and challenges for ubiquitous self-powered IOT systems deployment. - Tanay Karnik (IGSC, 2018)

Density Tradeoffs of Non-Volatile Memory as a Replacement for SRAM Based Last Level Cache. - Kunal Korgaonkar; Ishwar Bhati; Huichu Liu; Jayesh Gaur; Sasikanth Manipatruni; Sreenivas Subramoney; Tanay Karnik; Steven Swanson; Ian Young 001; Hong Wang 003 (ISCA, 2018)

A cm-scale self-powered intelligent and secure IoT edge mote featuring an ultra-low-power SoC in 14nm tri-gate CMOS. - Tanay Karnik; Dileep Kurian; Paolo A. Aseron; Richard Dorrance; Erkan Alpman; Angela Nicoara; Roman Popov; Leonid Azarenkov; Mikhail J. Moiseev; Li Zhao 002; Santosh Ghosh; Rafael Misoczki; et al. (ISSCC, 2018)

A Single-Stage, Single-Inductor, 6-Input 9-Output Multi-Modal Energy Harvesting Power Management IC for 100µW-120MW Battery-Powered IoT Edge Nodes. - Suhwan Kim 002; Vaibhav A. Vaidya; Christopher Schaef; Andrew Lines; Harish Krishnamurthy; Sheldon Weng; Xiaosen Liu; Dileep Kurian; Tanay Karnik; Krishnan Ravichandran; James W. Tschanz; Vivek De (VLSI Circuits, 2018)

Low-Power, Adaptive Neuromorphic Systems: Recent Progress and Future Directions. - Arindam Basu; Jyotibdha Acharya; Tanay Karnik; Huichu Liu; Hai Helen Li; Jae-sun Seo; Chang Song 001 (IEEE J. Emerg. Sel. Topics Circuits Syst., 2018)

Guest Editorial Low-Power, Adaptive Neuromorphic Systems: Devices, Circuit, Architectures and Algorithms. - Arindam Basu; Meng-Fan Chang; Elisabetta Chicca; Tanay Karnik; Hai Helen Li; Jae-sun Seo (IEEE J. Emerg. Sel. Topics Circuits Syst., 2018)

Hierarchical Design Methodology and Optimization for Proximity Communication based Contactless 3D ThruChip Interface. - Srinivasan Gopal; Deukhyoun Heo; Tanay Karnik (3DIC, 2019)

Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. - Massimo Alioto; Magdy S. Abadir; Tughrul Arslan; Chirn Chye Boon; Andreas Burg 001; Chip-Hong Chang; Meng-Fan Chang; Yao-Wen Chang; Poki Chen; Pasquale Corsonello; Paolo Crovetti; Shiro Dosho; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Self-Powered IOT System for Edge Inference. - Dileep Kurian; Tanay Karnik; Saksham Soni; Saransh Chhabra; Suhwan Kim 002; Jaykant Timbadiya; Ankit Gupta 011; Krishnan Ravichandran; Mukesh Bhartiya; Angela Nicoara (ISQED, 2020)

A 93 TOPS/Watt Near-Memory Reconfigurable SAD Accelerator for HEVC/AV1/JEM Encoding. - Jainaveen Sundaram; Srivatsa Rangachar Srinivasa; Dileep Kurian; Indranil Chakraborty; Sirisha Rani Kale; Nilesh Jain; Tanay Karnik; Ravi R. Iyer 001; Anuradha Srinivasan (DATE, 2021)

Trends and Opportunities for SRAM Based In-Memory and Near-Memory Computation. - Srivatsa Srinivasa; Akshay Krishna Ramanathan; Jainaveen Sundaram; Dileep Kurian; Srinivasan Gopal; Nilesh Jain; Anuradha Srinivasan; Ravi R. Iyer 001; Vijaykrishnan Narayanan; Tanay Karnik (ISQED, 2021)

F1: Striking the Balance Between Energy Efficiency & Flexibility: General-Purpose vs Special-Purpose ML Processors. - Sukhwan Lim; Yongpan Liu; Luca Benini; Tanay Karnik; Hsie-Chia Chang (ISSCC, 2021)

Recent Advances and Future Challenges in 2.5D/3D Heterogeneous Integration (Invited). - Tanay Karnik (SLIP, 2021)

Innovations for Intelligent Edge. - Vida Ilderem; Stefano Pellerano; Jim Tschanz; Tanay Karnik; Vivek De (ESSCIRC, 2022)

Resonant Rotary Clock Synchronization with Active and Passive Silicon Interposer. - Ragh Kuttappa; Baris Taskin; Vinayak Honkote; Satish Yada; Jainaveen Sundaram; Dileep Kurian; Tanay Karnik; Anuradha Srinivasan (ISCAS, 2022)

Recent Advances and Future Challenges in 2.5D/3D Heterogeneous Integration. - Tanay Karnik (ISPD, 2022)

Design Methodology for Scalable 2.5D/3D Heterogenous Tiled Chiplet Systems. - Srivatsa Rangachar Srinivasa; Jainaveen Sundaram Priya; Dileep Kurian; Erika Ramirez Lozano; Satish Yada; Saransh Chhabra; Kamakhya Prasad Sahu; Paolo A. Aseron; Ronald Kalim; Anuradha Srinivasan; Tanay Karnik (ISQED, 2022)

Introduction to the Special Section on the 2021 IEEE International Solid-State Circuits Conference (ISSCC). - Amir Amirkhany; Tanay Karnik; Shidhartha Das; Jun Deguchi; Yasuhiko Taito (IEEE J. Solid State Circuits, 2022)

CPU Microarchitectural Performance Analysis of SVT-AV1 Encoder. - Prerna Budhkar; Navneet Rao; Jainaveen Sundaram; Tanay Karnik (ICIP, 2023)

On Continuing DNN Accelerator Architecture Scaling Using Tightly Coupled Compute-on-Memory 3-D ICs. - Gauthaman Murali; Aditya Iyer 001; Lingjun Zhu; Jianming Tong; Francisco Muñoz-Martínez; Srivatsa Rangachar Srinivasa; Tanay Karnik; Tushar Krishna; Sung Kyu Lim (IEEE Trans. Very Large Scale Integr. Syst., 2023)

A 3.2GHz-15GHz Low Jitter Resonant Clock Featuring Rotary Traveling Wave Oscillators in Intel 4 CMOS for 3D Heterogeneous Multi-Die Systems. - Vinayak Honkote; Ragh Kuttappa; Jainaveen Sundaram; Satish Yada; Chinnusamy Kalimuthu; Juhi Patil; Richard Lee; Cristan Paulino; Paolo A. Aseron; Trang Nguyen; Amreesh Rao; Dileep Kurian; et al. (VLSI Technology and Circuits, 2024)

A High-Performance Passive Base System for Distributed AI/Media Acceleration. - Ragh Kuttappa; Jainaveen Sundaram; Srivatsa Rangachar Srinivasa; Paolo A. Aseron; Gauthaman Murali; Vinayak Honkote; Prerna Budhkar; Dileep Kurian; Ronald Kalim; Thomas P. Thomas; Anuradha Srinivasan; Tanay Karnik (CICC, 2025)

A 68 TOPS/W, 256MB SRAM Sparse GEMM Accelerator Tiled Across 16, 4nm Near Memory Compute (NMC) Chiplets Disaggregated 2.5D System. - Srivatsa Rangachar Srinivasa; Prerna Budhkar; Gauthaman Murali; Vui Seng Chua; Paolo A. Aseron; Vinayak Honkote; Ravi R. Iyer 001; Nilesh Jain; Dileep John Kurian; Anuradha Srinivasan; Tanay Karnik (CICC, 2025)

System-Level Validation Across Multiple Platforms to build a Robust 2.5D Multi Foundry Chiplet Solution. - Srivatsa Rangachar Srinivasa; Dileep Kurian; Paolo A. Aseron; Prerna Budhkar; Vinayak Honkote; Dan Lake; Jaykant Timbadiya; Satish Yada; Suresh Kadavakollu; James Greensky; Gauthaman Murali; Anuradha Srinivasan; et al. (ACM Great Lakes Symposium on VLSI, 2025)

A 300MB SRAM, 20Tb/s Bandwidth Scalable Heterogenous 2.5D System Inferencing Simultaneous Streams Across 20 Chiplets with Workload-Dependent Configurations. - Srivatsa Rangachar Srinivasa; Dileep Kurian; Paolo A. Aseron; Prerna Budhkar; Arun Radhakrishnan; Alejandro Cardenas Lopez; Jainaveen Sundaram; Vinayak Honkote; Leonid Azarenkov; Dan Lake; Jaykant Timbadiya; Mikhail J. Moiseev; et al. (ISSCC, 2025)