A Bit-Serial, Compute-in-SRAM Design Featuring Hybrid-Integrating ADCs and Input Dependent Binary Scaled Precharge Eliminating DACs for Energy-Efficient DNN Inference. - Rishabh Sehgal; Tanmay Thareja; Shanshan Xie; Can Ni; Jaydeep P. Kulkarni (IEEE J. Solid State Circuits, 2023)