Testing of 3D IC with minimum power using genetic algorithm. - Tanusree Kaibartta; Debesh K. Das (IDT, 2015)

Optimization of Test Wrapper Length for TSV Based 3D SOCs Using a Heuristic Approach. - Tanusree Kaibartta; Debesh Kumar Das (VDAT, 2018)

Approach of genetic algorithm for power-aware testing of 3D IC. - Tanusree Kaibartta; Chandan Giri; Hafizur Rahaman 001; Debesh Kumar Das (IET Comput. Digit. Tech., 2019)

Heuristic Approach for Identification of Random TSV Defects in 3D IC During Pre-bond Testing. - Tanusree Kaibartta; G. P. Biswas; Debesh K. Das (ATS, 2020)

Co-Optimization of Test Wrapper Length and TSV for TSV Based 3D SOCs. - Tanusree Kaibartta; G. P. Biswas; Debesh Kumar Das (J. Electron. Test., 2020)

A Genetic Algorithm-Based Metaheuristic Approach for Test Cost Optimization of 3D SIC. - Tanusree Kaibartta; G. P. Biswas; Arup Kumar Pal; Debesh Kumar Das (IEEE Access, 2021)

A Novel TSV Repair Framework for 3-D Stacked ICs. - Tanusree Kaibartta; Rajiv Murmu; Debesh Kumar Das (ATS, 2024)

Genetic Algorithm Based Efficient Grouping Technique for Post Bond Test and Crosstalk Faults Among TSVs. - Tanusree Kaibartta; Hitarth Arora; Debesh Kumar Das (VLSID, 2024)