Chip-level characterization and RTN-induced error mitigation beyond 20nm floating gate flash memory. - T. W. Lin; S. H. Ku; C. H. Cheng; C. W. Lee; Ijen Huang; Wen-Jer Tsai; Tao-Cheng Lu; W. P. Lu; Kuang-Chao Chen; Tahui Wang; Chih-Yuan Lu (IRPS, 2018)

Investigation of data pattern effects on nitride charge lateral migration in a charge trap flash memory by using a random telegraph signal method. - Y. H. Liu; H. Y. Lin; C. M. Jiang; Tahui Wang; Wen-Jer Tsai; Tao-Cheng Lu; Kuang-Chao Chen; Chih-Yuan Lu (IRPS, 2018)

A Page-Buffer and Fail-Bit Counter-Based In-Memory Computing Platform for 3-D NAND Flash Memory. - Wen-Jer Tsai; Chun-Chang Lu; Ting-En Hsieh; Tao-Cheng Lu; Kuang-Chao Chen; Tuo-Hung Hou; Chih-Yuan Lu (IEEE J. Emerg. Sel. Topics Circuits Syst., 2026)