Comparison of On-die Global Clock Distribution Methods for Parallel Serial Links. - Kangmin Hu; Tao Jiang 005; Patrick Chiang 001 (ISCAS, 2009)

Sense Amplifier Power and Delay Characterization for Operation under Low-Vdd and Low-voltage Clock Swing. - Tao Jiang 005; Patrick Yin Chiang (ISCAS, 2009)

Single-channel, 1.25-GS/s, 6-bit, loop-unrolled asynchronous SAR-ADC in 40nm-CMOS. - Tao Jiang 005; Wing Liu; Freeman Y. Zhong; Charlie Zhong; Patrick Yin Chiang (CICC, 2010)

A 0.6 mW/Gb/s, 6.4-7.2 Gb/s Serial Link Receiver Using Local Injection-Locked Ring Oscillators in 90 nm CMOS. - Kangmin Hu; Tao Jiang 005; Jingguang Wang; Frank O'Mahony; Patrick Yin Chiang (IEEE J. Solid State Circuits, 2010)

Low-power 8Gb/s near-threshold serial link receivers using super-harmonic injection locking in 65nm CMOS. - Kangmin Hu; Tao Jiang 005; Samuel Palermo; Patrick Yin Chiang (CICC, 2011)

A low-power, capacitively-divided, ring oscillator with digitally adjustable voltage swing. - Tao Jiang 005; Kangmin Hu; Patrick Yin Chiang (VLSI-DAT, 2012)

0.16-0.25 pJ/bit, 8 Gb/s Near-Threshold Serial Link Receiver With Super-Harmonic Injection-Locking. - Kangmin Hu; Rui Bai 001; Tao Jiang 005; Chao Ma 020; Ahmed Ragab; Samuel Palermo; Patrick Yin Chiang (IEEE J. Solid State Circuits, 2012)

A Single-Channel, 1.25-GS/s, 6-bit, 6.08-mW Asynchronous Successive-Approximation ADC With Improved Feedback Delay in 40-nm CMOS. - Tao Jiang 005; Wing Liu; Freeman Y. Zhong; Charlie Zhong; Kangmin Hu; Patrick Yin Chiang (IEEE J. Solid State Circuits, 2012)