A Scalable Deadlock-Free Static Routing Algorithm for Chiplet-Based Systems. - Xiaoran Zhang; Mingyu Wang 003; Yicong Zhang; Tao Lu 012; Zhiyi Yu (ICPADS, 2023)

CINOC: Computing in Network-On-Chip With Tiled Many-Core Architectures for Large-Scale General Matrix Multiplications. - Yao Qin; Mingyu Wang 003; Jiahua Yan; Tao Lu 012; Zhiyi Yu (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

A Hybrid CAM-SRAM Processing-in-Memory Architecture With Feature Level Sparsity for Attention Mechanisms. - Haiqiu Huang; Mingyu Wang 003; Xiaojie Li; Baiqing Zhong; Zeqi Yang; Tao Lu 012; Yicong Zhang; Zhiyi Yu (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

NBCache: An Efficient and Scalable Non-Blocking Cache for Coherent Multi-Chiplet Systems. - Zhirong Ye; Yongchang Zhang; Peilin Wang; Tao Lu 012; Zhaolin Li; Zhiyi Yu; Mingyu Wang 003 (ASP-DAC, 2026)

UniCNet: Unified Cycle-Accurate Simulation for Composable Chiplet Network With Modular Design-Integration Workflow. - Peilin Wang; Mingyu Wang 003; Zhirong Ye; Tao Lu 012; Zhiyi Yu (IEEE Comput. Archit. Lett., 2026)

FSMA: Fine-Grained Interlayer Scheduling and Mapping Co-Exploration Framework for Chiplet-Based DNN Accelerators. - Tao Lu 012; Yongchang Zhang; Peilin Wang; Haiqiu Huang; Zhirong Ye; Mingyu Wang 003 (IEEE Embed. Syst. Lett., 2026)