A near threshold error resilient processor based on dynamic timing error prediction and within-a-cycle timing error correction. - Tao-Tao Zhu; Xiaoyan Xiang; Chen Chen 058; Jianyi Meng (ASICON, 2015)

SGERC: a self-gated timing error resilient cluster of sequential cells for wide-voltage processor. - Tao-Tao Zhu; Xiaoyan Xiang; Chen Chen 058; Jianyi Meng (IEICE Electron. Express, 2017)

Eliminating Timing Errors Through Collaborative Design to Maximize the Throughput. - Zhan-Hui Li; Tao-Tao Zhu; Zhi-Jian Chen; Jian-Yi Meng; Xiaoyan Xiang; Xiaolang Yan (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Error-Resilient Integrated Clock Gate for Clock-Tree Power Optimization on a Wide Voltage IOT Processor. - Tao-Tao Zhu; Jian-Yi Meng; Xiaoyan Xiang; Xiaolang Yan (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A low power QRS detection processor with adaptive scaling of processing resolution. - Zhijian Chen; Menghan Jia; Jiahui Luo; Tao-Tao Zhu; Xiaoyan Xiang; Jianyi Meng (IEICE Electron. Express, 2018)

ECG-Based Heartbeat Classification Using Two-Level Convolutional Neural Network and RR Interval Difference. - Yande Xiang; Jiahui Luo; Tao-Tao Zhu; Sheng Wang 005; Xiaoyan Xiang; Jianyi Meng (IEICE Trans. Inf. Syst., 2018)

Low-power perceptron model based ECG processor for premature ventricular contraction detection. - Zhijian Chen; Huanzhang Xu; Jiahui Luo; Tao-Tao Zhu; Jianyi Meng (Microprocess. Microsystems, 2018)

An Energy-Efficient ECG Processor With Weak-Strong Hybrid Classifier for Arrhythmia Detection. - Zhijian Chen; Jiahui Luo; Kaiwen Lin; Jiaquan Wu; Tao-Tao Zhu; Xiaoyan Xiang; Jianyi Meng (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A Dedicated Greedy Short Path Padding Solution Method for Error Resilient Circuit Designs. - Yan He; Zhijian Chen; Xiaoyan Xiang; Tao-Tao Zhu (IEEE Access, 2020)