Tao Zhang

Affiliations:

NVIDIA Corporation, Santa Clara, CA, USA
Pennsylvania State University, Department of Computer Science and Engineering, PA, USA (former)

According to our database¹, Tao Zhang authored at least 25 papers between 2009 and 2022.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

Legend:

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In proceedings

Article

PhD thesis

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Links

On csauthors.net:

Bibliography

2022

Flatfish: A Reinforcement Learning Approach for Application-Aware Address Mapping.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2019

RC-NVM: Dual-Addressing Non-Volatile Memory Architecture Supporting Both Row and Column Memory Accesses.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2019

Sparse Tensor Core: Algorithm and Hardware Co-Design for Vector-wise Sparse Neural Networks on Modern GPUs.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

2018

RC-NVM: Enabling Symmetric Row and Column Memory Accesses for In-memory Databases.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

2016

BACH: A Bandwidth-Aware Hybrid Cache Hierarchy Design with Nonvolatile Memories.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2016

Building a Low Latency, Highly Associative DRAM Cache with the Buffered Way Predictor.

[BibT_eX]

[DOI]

Proceedings of the 28th International Symposium on Computer Architecture and High Performance Computing, 2016

PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory.

[BibT_eX]

[DOI]

Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

Fine-granularity tile-level parallelism in non-volatile memory architecture with two-dimensional bank subdivision.

[BibT_eX]

[DOI]

Matthew Poremba

Tao Zhang

Yuan Xie

Proceedings of the 53rd Annual Design Automation Conference, 2016

2015

NVMain 2.0: A User-Friendly Memory Simulator to Model (Non-)Volatile Memory Systems.

[BibT_eX]

[DOI]

Matthew Poremba

Tao Zhang

Yuan Xie

IEEE Comput. Archit. Lett., 2015

Overcoming the challenges of crossbar resistive memory architectures.

[BibT_eX]

[DOI]

Cong Xu

Dimin Niu

Naveen Muralimanohar

Rajeev Balasubramonian

Tao Zhang

Shimeng Yu

Yuan Xie

Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

2014

Half-DRAM: A high-bandwidth and low-power DRAM architecture from the rethinking of fine-grained activation.

[BibT_eX]

[DOI]

Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

Using multi-level cell STT-RAM for fast and energy-efficient local checkpointing.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

CREAM: A Concurrent-Refresh-Aware DRAM Memory architecture.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

TSV power supply array electromigration lifetime analysis in 3D ICS.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

3D-SWIFT: a high-performance 3D-stacked wide IO DRAM.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

2013

Lazy Precharge: An overhead-free method to reduce precharge overhead for memory parallelism improvement of DRAM system.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Thermomechanical stress-aware management for 3D IC designs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

An efficient run-time encryption scheme for non-volatile main memory.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Compilers, 2013

2011

MorphCache: A Reconfigurable Adaptive Multi-level Cache hierarchy.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011

Using NEM relay to improve 3DIC cost efficiency.

[BibT_eX]

[DOI]

Tao Zhang

Guangyu Sun

Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

2010

A customized design of DRAM controller for on-chip 3D DRAM stacking.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

A 3D SoC design for H.264 application with on-chip DRAM stacking.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on 3D System Integration, 2010

2009

CheckerCore: enhancing an FPGA soft core to capture worst-case execution times.

[BibT_eX]

[DOI]

Jin Ouyang

Raghuveer Raghavendra

Proceedings of the 2009 International Conference on Compilers, 2009

Arithmetic unit design using 180nm TSV-based 3D stacking technology.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on 3D System Integration, 2009

Investigation and comparison of thermal distribution in synchronous and asynchronous 3D ICs.

[BibT_eX]

[DOI]

Brent Hollosi

Tao Zhang

Ravi Sankar Parameswaran Nair

Yuan Xie

Jia Di

Scott C. Smith

Proceedings of the IEEE International Conference on 3D System Integration, 2009

Tao Zhang

Timeline

Legend:

Links

On csauthors.net:

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