Enabling in-situ logic-in-memory capability using resistive-RAM crossbar memory. - Naifeng Jing; Taozhong Li; Zhongyuan Zhao 004; Wei Jin 004; Yanan Sun 003; Weifeng He; Zhigang Mao (FPT, 2016)

A Novel Resistive Memory-based Process-in-memory Architecture for Efficient Logic and Add Operations. - Taozhong Li; Qin Wang 009; Yongxin Zhu 001; Jianfei Jiang 001; Guanghui He; Jing Jin 005; Zhigang Mao; Naifeng Jing (ACM Trans. Design Autom. Electr. Syst., 2019)

Enabling Resistive-RAM-based Activation Functions for Deep Neural Network Acceleration. - Zihan Zhang; Taozhong Li; Ning Guan; Qin Wang 009; Guanghui He; Weiguang Sheng; Zhigang Mao; Naifeng Jing (ACM Great Lakes Symposium on VLSI, 2020)

A Hybrid-Grained Remapping Defense Scheme Against Hard Failures for Row-Column-NVM. - Taozhong Li; Naifeng Jing; Zhigang Mao; Yiran Chen 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

A Novel Architecture Design for Output Significance Aligned Flow with Adaptive Control in ReRAM-based Neural Network Accelerator. - Taozhong Li; Naifeng Jing; Jianfei Jiang 001; Qin Wang 009; Zhigang Mao; Yiran Chen 001 (ACM Trans. Design Autom. Electr. Syst., 2022)