On Behavior Fault Modeling for Combinational Digital Designs. - Tapan J. Chakraborty; Sumit Ghosh (ITC, 1988)

Gentest: An Automatic Test-Generation System for Sequential Circuits. - Wu-Tung Cheng; Tapan J. Chakraborty (Computer, 1989)

Enhanced Controllability for IDDQ Test Sets Using Partial Scan. - Tapan J. Chakraborty; Sudipta Bhawmik; Robert Bencivenga; Chih-Jen Lin (DAC, 1991)

On behavior fault modeling for digital designs. - Sumit Ghosh; Tapan J. Chakraborty (J. Electron. Test., 1991)

Delay Fault Models and Test Generation for Random Logic Sequential Circuits. - Tapan J. Chakraborty; Vishwani D. Agrawal; Michael L. Bushnell (DAC, 1992)

Design for Testability for Path Delay faults in Sequential Circuits. - Tapan J. Chakraborty; Vishwani D. Agrawal; Michael L. Bushnell (DAC, 1993)

Partial scan testing with single clock control. - Vishwani D. Agrawal; Tapan J. Chakraborty (VTS, 1993)

Delay independent initialization of sequential circuits. - Tapan J. Chakraborty; Vishwani D. Agrawal (Great Lakes Symposium on VLSI, 1994)

High-Performance Circuit Testing with Slow-Speed Testers. - Vishwani D. Agrawal; Tapan J. Chakraborty (ITC, 1995)

Robust testing for stuck-at faults. - Tapan J. Chakraborty; Vishwani D. Agrawal (VLSI Design, 1995)

Simulation of at-speed tests for stuck-at faults. - Tapan J. Chakraborty; Vishwani D. Agrawal (VTS, 1995)

Design for high-speed testability of stuck-at faults. - Tapan J. Chakraborty; Vishwani D. Agrawal (VLSI Design, 1996)

Effective Path Selection for Delay Fault Testing of Sequential Circuits. - Tapan J. Chakraborty; Vishwani D. Agrawal (ITC, 1997)

On variable clock methods for path delay testing of sequential circuits. - Tapan J. Chakraborty; Vishwani D. Agrawal; Michael L. Bushnell (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

A BIST scheme for the detection of path-delay faults. - Nilanjan Mukherjee 001; Tapan J. Chakraborty; Sudipta Bhawmik (ITC, 1998)

Built in self test: a complete test solution for telecommunication systems. - Nilanjan Mukherjee 001; Tapan J. Chakraborty; Ramesh Karri (IEEE Commun. Mag., 1999)

Path delay fault simulation of sequential circuits. - Tapan J. Chakraborty; Vishwani D. Agrawal; Michael L. Bushnell (IEEE Trans. Very Large Scale Integr. Syst., 2000)

Improving path delay testability of sequential circuits. - Tapan J. Chakraborty; Vishwani D. Agrawal; Michael L. Bushnell (IEEE Trans. Very Large Scale Integr. Syst., 2000)

A Novel Fault Injection Method for System Verification Based on FPGA Boundary Scan Architectur. - Tapan J. Chakraborty; Chen-Huan Chiang (ITC, 2002)

Efficient Test Architecture based on Boundary Scan for Comprehensive System Test. - Tapan J. Chakraborty (Asian Test Symposium, 2005)

A TMR Scheme for SEU Mitigation in Scan Flip-Flops. - Roystein Oliveira; Aditya Jagirdar; Tapan J. Chakraborty (ISQED, 2007)

A practical approach to comprehensive system test & debug using boundary scan based test architecture. - Tapan J. Chakraborty; Chen-Huan Chiang; Bradford G. Van Treuren (ITC, 2007)

FPGA Prototyping of a Scan Based System-On-Chip Design. - Brendan Mullane; Chen-Huan Chiang; Michael Higgins; Ciaran MacNamee; Tapan J. Chakraborty; Thomas B. Cook (ReCoSoC, 2007)

A New Language Approach for IJTAG. - Michele Portolan; Suresh Goyal; Bradford G. Van Treuren; Chen-Huan Chiang; Tapan J. Chakraborty; Thomas B. Cook (ITC, 2008)

A Robust Architecture for Flip-Flops Tolerant to Soft-Errors and Transients from Combinational Circuits. - Aditya Jagirdar; Roystein Oliveira; Tapan J. Chakraborty (VLSI Design, 2008)

A Common Language Framework for Next-Generation Embedded Testing. - Michele Portolan; Suresh Goyal; Bradford G. Van Treuren; Chen-Huan Chiang; Tapan J. Chakraborty; Thomas B. Cook (IEEE Des. Test Comput., 2010)

Functional Fmax test-time reduction using novel DFTs for circuit initialization. - Ujjwal Guin; Tapan J. Chakraborty; Mohammad Tehranipoor (ICCD, 2013)