Block-wise Extraction of Rent's Exponents for an Extensible Processor. - Tapani Ahonen; Tero Nurmi; Jari Nurmi; Jouni Isoaho (ISVLSI, 2003)

Design reuse and design for reuse, a case study on HDSL2. - Tapani Ahonen; Jari Nurmi (SoC, 2004)

A synthesizable RTL design of asynchronous FIFO. - Xin Wang; Tapani Ahonen; Jari Nurmi (SoC, 2004)

Topology optimization for application-specific networks-on-chip. - Tapani Ahonen; David A. Sigüenza-Tortosa; Hong Bin; Jari Nurmi (SLIP, 2004)

Issues in the development of a practical NoC: the Proteo concept. - David A. Sigüenza-Tortosa; Tapani Ahonen; Jari Nurmi (Integr., 2004)

Integration of a NoC-Based Multimedia Processing Platform. - Tapani Ahonen; Jari Nurmi (FPL, 2005)

Prototyping a Globally Asynchronous Locally Synchronous Network-On-Chip on a Conventional FPGA Device Using Synchronous Design Tools. - Xin Wang; Tapani Ahonen; Jari Nurmi (FPL, 2006)

Applying CDMA Technique to Network-on-Chip. - Xin Wang; Tapani Ahonen; Jari Nurmi (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Design space exploration of an open-source, IP-reusable, scalable floating-point engine for embedded applications. - Claudio Brunelli; Fabio Campi; Claudio Mucci; Davide Rossi; Tapani Ahonen; Juha Kylliäinen; Fabio Garzia; Jari Nurmi (J. Syst. Archit., 2008)

Implementation of W-CDMA Cell Search on a FPGA Based Multi-Processor System-on-Chip with Power Management. - Roberto Airoldi; Fabio Garzia; Tapani Ahonen; Dragomir Milojevic; Jari Nurmi (SAMOS, 2009)

Implementation of the W-CDMA cell search on a MPSOC designed for software defined radios. - Fabio Garzia; Roberto Airoldi; Tapani Ahonen; Jari Nurmi; Dragomir Milojevic (SiPS, 2009)

Multicore Software-Defined Radio Architecture for GNSS Receiver Signal Processing. - Heikki Hurskainen; Jussi Raasakka; Tapani Ahonen; Jari Nurmi (EURASIP J. Embed. Syst., 2009)

Application-driven dimensioning of a Coarse-Grain Reconfigurable Array. - Waqar Hussain 001; Tapani Ahonen; Fabio Garzia; Jari Nurmi (AHS, 2011)

State of the art baseband DSP platforms for Software Defined Radio: A survey. - Omer Anjum; Tapani Ahonen; Fabio Garzia; Jari Nurmi; Claudio Brunelli; Heikki Berg (EURASIP J. Wirel. Commun. Netw., 2011)

Implementation of W-CDMA Cell Search on a Highly Parallel and Scalable MPSoC. - Roberto Airoldi; Tapani Ahonen; Fabio Garzia; Dragomir Milojevic; Jari Nurmi (J. Signal Process. Syst., 2011)

Reconfigurable multi-processor architecture for streaming applications. - Leyla S. Ghazanfari; Roberto Airoldi; Jari Nurmi; Tapani Ahonen (FPL, 2012)

Effects of scaling a coarse-grain reconfigurable array on power and energy consumption. - Waqar Hussain 001; Tapani Ahonen; Jari Nurmi (ISSoC, 2012)

Energy and power estimation of Coarse-Grain Reconfigurable Array based Fast Fourier Transform accelerators. - Waqar Hussain 001; Tapani Ahonen; Roberto Airoldi; Jari Nurmi (ReCoSoC, 2012)

Designing Fast Fourier Transform Accelerators for Orthogonal Frequency-Division Multiplexing Systems. - Waqar Hussain 001; Fabio Garzia; Tapani Ahonen; Jari Nurmi (J. Signal Process. Syst., 2012)

Evaluation of WCDMA receiver baseband processing on a Multi-Processor System-On-Chip. - Rizwan Fazal; Waqar Hussain 001; Tapani Ahonen; Jari Nurmi (DSP, 2013)

A LLVM based compiler for COFFEE. - Guoqing Zhang; Tapani Ahonen (ISORC, 2013)

Design of an accelerator-rich architecture by integrating multiple heterogeneous coarse grain reconfigurable arrays over a network-on-chip. - Waqar Hussain 001; Roberto Airoldi; Henry Hoffmann; Tapani Ahonen; Jari Nurmi (ASAP, 2014)

FPGA implementation of a flexible synchronizer for cognitive radio applications. - Farid Shamani; Roberto Airoldi; Tapani Ahonen; Jari Nurmi (DASIP, 2014)

Constraint-driven frequency scaling in a Coarse Grain Reconfigurable Array. - Waqar Hussain 001; Henry Hoffmann; Tapani Ahonen; Jari Nurmi (ISSoC, 2014)

MPSoC based on Transport Triggered Architecture for baseband processing of an LTE receiver. - Omer Anjum; Tapani Ahonen; Jari Nurmi (J. Syst. Archit., 2014)

Design of a hybrid multicore platform for high performance reconfigurable computing. - Waqar Hussain 001; Henry Hoffmann; Tapani Ahonen; Jari Nurmi (NORCAS, 2015)

Design, implementation and analysis of a run-time configurable Memory Management Unit on FPGA. - Farid Shamani; Vida Fakour Sevom; Jari Nurmi; Tapani Ahonen (NORCAS, 2015)

FPGA implementation and integration of a reconfigurable CAN-based co-processor to the coffee risc processor. - Farid Shamani; Vida Fakour Sevom; Tapani Ahonen; Jari Nurmi (NORCAS, 2016)

Accelerating Computation on an Android Phone with OpenCL Parallelism and Optimizing Workload Distribution between a Phone and a Cloud Service. - Kui Wang; Jari Nurmi; Tapani Ahonen (UIC/ATC/ScalCom/CBDCom/IoP/SmartWorld, 2016)

HARP2: An X-Scale Reconfigurable Accelerator-Rich Platform for Massively-Parallel Signal Processing Algorithms. - Waqar Hussain 001; Roberto Airoldi; Henry Hoffmann; Tapani Ahonen; Jari Nurmi (J. Signal Process. Syst., 2016)

FPGA Implementation Issues of a Flexible Synchronizer Suitable for NC-OFDM-Based Cognitive Radios. - Farid Shamani; Roberto Airoldi; Vida Fakour Sevom; Tapani Ahonen; Jari Nurmi (J. Syst. Archit., 2017)

Integration issues of a run-time configurable memory management unit to a RISC processor on FPGA. - Farid Shamani; Vida Fakour Sevom; Tapani Ahonen; Jari Nurmi (Microprocess. Microsystems, 2017)

Power Mitigation by Performance Equalization in a Heterogeneous Reconfigurable Multicore Architecture. - Waqar Hussain 001; Henry Hoffmann; Tapani Ahonen; Jari Nurmi (J. Signal Process. Syst., 2017)