An Integrated Digital Architecture for the Real-time Reconstruction in a VSiP Sensor. - Anthony Kolar; Tarik Graba; Andréa Pinna 001; Olivier Romain; Bertrand Granado; Thomas Ea (ICECS, 2006)

Place-and-Route Impact on the Security of DPL Designs in FPGAs. - Sylvain Guilley; Sumanta Chaudhuri; Jean-Luc Danger; Laurent Sauvage; Philippe Hoogvorst; Maxime Nassar; Tarik Graba; Vinh-Nga Vong (HOST, 2008)

Evaluation of Power-Constant Dual-Rail Logic as a Protection of Cryptographic Applications in FPGAs. - Sylvain Guilley; Laurent Sauvage; Jean-Luc Danger; Tarik Graba; Yves Mathieu (SSIRI, 2008)

WDDL is Protected against Setup Time Violation Attacks. - Nidhal Selmane; Shivam Bhasin; Sylvain Guilley; Tarik Graba; Jean-Luc Danger (FDTC, 2009)

Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow. - Shivam Bhasin; Jean-Luc Danger; Florent Flament; Tarik Graba; Sylvain Guilley; Yves Mathieu; Maxime Nassar; Laurent Sauvage; Nidhal Selmane (ReConFig, 2009)

A System for an Accurate 3D Reconstruction in Video Endoscopy Capsule. - Anthony Kolar; Olivier Romain; Jade Ayoub; David Faura; Sylvain Viateur; Bertrand Granado; Tarik Graba (EURASIP J. Embed. Syst., 2009)

Efficient Dual-Rail Implementations in FPGA Using Block RAMs. - Shivam Bhasin; Sylvain Guilley; Youssef Souissi; Tarik Graba; Jean-Luc Danger (ReConFig, 2011)

A Small and High-Performance Coprocessor for Fingerprint Match-on-Card. - Taoufik Chouta; Jean-Luc Danger; Laurent Sauvage; Tarik Graba (DSD, 2012)

FPGA Design of an Open-Loop True Random Number Generator. - Florent Lozach; Molka Ben-Romdhane; Tarik Graba; Jean-Luc Danger (DSD, 2013)

Design methodology of an ASIC TRNG based on an open-loop delay chain. - Molka Ben-Romdhane; Tarik Graba; Jean-Luc Danger; Yves Mathieu (NEWCAS, 2013)

Stochastic Model of a Metastability-Based True Random Number Generator. - Molka Ben-Romdhane; Tarik Graba; Jean-Luc Danger (TRUST, 2013)

Studying Leakages on an Embedded Biometric System Using Side Channel Analysis. - Maël Berthier; Yves Bocktaels; Julien Bringer; Hervé Chabanne; Taoufik Chouta; Jean-Luc Danger; Mélanie Favre; Tarik Graba (COSADE, 2014)

Physical Security Evaluation at an Early Design-Phase: A Side-Channel Aware Simulation Methodology. - Shivam Bhasin; Jean-Luc Danger; Tarik Graba; Yves Mathieu; Daisuke Fujimoto; Makoto Nagata (ES4CPS@DATE, 2014)

Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical security. - Emna Amouri; Shivam Bhasin; Yves Mathieu; Tarik Graba; Jean-Luc Danger; Habib Mehrez (FPL, 2014)

A look into SIMON from a side-channel perspective. - Shivam Bhasin; Tarik Graba; Jean-Luc Danger; Zakaria Najm (HOST, 2014)

Cryptographically secure shields. - Jean-Michel Cioranesco; Jean-Luc Danger; Tarik Graba; Sylvain Guilley; Yves Mathieu; David Naccache; Xuan Thuy Ngo (HOST, 2014)

Side channel analysis on an embedded hardware fingerprint biometric comparator & low cost countermeasures. - Taoufik Chouta; Tarik Graba; Jean-Luc Danger; Julien Bringer; Maël Berthier; Yves Bocktaels; Mélanie Favre; Hervé Chabanne (HASP@ISCA, 2014)

Studying Potential Side Channel Leakages on an Embedded Biometric Comparison System. - Maël Berthier; Yves Bocktaels; Julien Bringer; Hervé Chabanne; Taoufik Chouta; Jean-Luc Danger; Mélanie Favre; Tarik Graba (IACR Cryptol. ePrint Arch., 2014)

Countering early propagation and routing imbalance of DPL designs in a tree-based FPGA. - Emna Amouri; Shivam Bhasin; Yves Mathieu; Tarik Graba; Jean-Luc Danger (ICICDT, 2015)

Hardware implementation of all digital calibration for undersampling TIADCs. - Han Le Duc; Duc Minh Nguyen; Chadi Jabbour; Tarik Graba; Patricia Desgreys; Olivier Jamin; Van Tam Nguyen 004 (ISCAS, 2015)

Sophisticated security verification on routing repaired balanced cell-based dual-rail logic against side channel analysis. - Wei He 015; Shivam Bhasin; Andrés Otero; Tarik Graba; Eduardo de la Torre; Jean-Luc Danger (IET Inf. Secur., 2015)

Multi-Valued Routing Tracks for FPGAs in 28nm FDSOI Technology. - Sumanta Chaudhuri; Tarik Graba; Yves Mathieu (CoRR, 2016)

All-Digital Calibration of Timing Skews for TIADCs Using the Polyphase Decomposition. - Han Le Duc; Duc Minh Nguyen; Chadi Jabbour; Tarik Graba; Patricia Desgreys; Olivier Jamin; Van Tam Nguyen 004 (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Multi-level formal verification - A new approach against fault injection attack. - Laurent Sauvage; Tarik Graba; Thibault Porteboeuf (J. Cryptogr. Eng., 2017)

Cryptographically Secure Shield for Security IPs Protection. - Xuan Thuy Ngo; Jean-Luc Danger; Sylvain Guilley; Tarik Graba; Yves Mathieu; Zakaria Najm; Shivam Bhasin (IEEE Trans. Computers, 2017)

Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology. - Jean-Luc Danger; Risa Yashiro; Tarik Graba; Yves Mathieu; Abdelmalek Si-Merabet; Kazuo Sakiyama; Noriyuki Miura; Makoto Nagata (DSD, 2018)

Generic Architecture for Lightweight Block Ciphers: A First Step Towards Agile Implementation of Multiple Ciphers. - Etienne Tehrani; Jean-Luc Danger; Tarik Graba (WISTP, 2018)

Classification of Lightweight Block Ciphers for Specific Processor Accelerated Implementations. - Etienne Tehrani; Tarik Graba; Abdelmalek Si-Merabet; Sylvain Guilley; Jean-Luc Danger (ICECS, 2019)

RISC-V Extension for Lightweight Cryptography. - Etienne Tehrani; Tarik Graba; Abdelmalek Si-Merabet; Jean-Luc Danger (DSD, 2020)

High Throughput/Gate AES Hardware Architectures Based on Datapath Compression. - Rei Ueno; Naofumi Homma; Sumio Morioka; Noriyuki Miura; Kohei Matsuda; Makoto Nagata; Shivam Bhasin; Yves Mathieu; Tarik Graba; Jean-Luc Danger (IEEE Trans. Computers, 2020)

RSM Protection of the PRESENT Lightweight Cipher as a RISC-V Extension. - Etienne Tehrani; Tarik Graba; Abdelmalek Si-Merabet; Jean-Luc Danger (DSD, 2021)

Diffusional Side-Channel Leakage From Unrolled Lightweight Block Ciphers: A Case Study of Power Analysis on PRINCE. - Ville Yli-Mäyry; Rei Ueno; Noriyuki Miura; Makoto Nagata; Shivam Bhasin; Yves Mathieu; Tarik Graba; Jean-Luc Danger; Naofumi Homma (IEEE Trans. Inf. Forensics Secur., 2021)

Jitter Compensation Mechanism for Dynamic Deterministic Networks. - Guillaume Soudais; Tarik Graba; Yves Mathieu; Sébastien Bigo (OFC, 2023)