Algebraic approach to arithmetic design verification. - Mohamed Abdul Basith; Tariq B. Ahmad; André Rossi; Maciej J. Ciesielski (FMCAD, 2011)

An Approach to Multi-core Functional Gate-Level Simulation Minimizing Synchronization and Communication Overheads. - Tariq Bashir Ahmad; Maciej J. Ciesielski (MTV, 2013)

Fast STA prediction-based gate-level timing simulation. - Tariq B. Ahmad; Maciej J. Ciesielski (DATE, 2014)

Fast time-parallel C-based event-driven RTL simulation. - Tariq Bashir Ahmad; Maciej J. Ciesielski (DDECS, 2014)

Parallel Multi-core Verilog HDL Simulation Using Domain Partitioning. - Tariq B. Ahmad; Maciej J. Ciesielski (ISVLSI, 2014)