1/5 power reduction by global optimization based on fine-grained body biasing. - Yasumi Nakamura; David Levacq; Limin Xiao; Takuya Minakawa; Taro Niiyama; Makoto Takamiya; Takayasu Sakurai (CICC, 2008)

Expected vectorless Teacher-Student Swap (TSS) test method with dual power supply voltages for 0.3V homogeneous multi-core LSI's. - Taro Niiyama; Koichi Ishida; Makoto Takamiya; Takayasu Sakurai (CICC, 2008)

Increasing minimum operating voltage (VDDmin) with number of CMOS logic gates and experimental verification with up to 1Mega-stage ring oscillators. - Taro Niiyama; Piao Zhe; Koichi Ishida; Masami Murakata; Makoto Takamiya; Takayasu Sakurai (ISLPED, 2008)

Dependence of Minimum Operating Voltage (VDDmin) on Block Size of 90-nm CMOS Ring Oscillators and its Implications in Low Power DFM. - Taro Niiyama; Piao Zhe; Koichi Ishida; Masami Murakata; Makoto Takamiya; Takayasu Sakurai (ISQED, 2008)

Difficulty of Power Supply Voltage Scaling in Large Scale Subthreshold Logic Circuits. - Tadashi Yasufuku; Taro Niiyama; Piao Zhe; Koichi Ishida; Masami Murakata; Makoto Takamiya; Takayasu Sakurai (IEICE Trans. Electron., 2010)

The Mapping Distance - a Generalization of the Edit Distance - and its Application to Trees. - Kilho Shin; Taro Niiyama (ICAART (2), 2018)

Parameterized Mapping Distances for Semi-Structured Data. - Kilho Shin 001; Taro Niiyama (ICAART (Revised Selected Papers), 2018)