Verification of design decisions in ForSyDe. - Tarvo Raudvere; Ingo Sander; Ashish Kumar Singh; Axel Jantsch (CODES+ISSS, 2003)

Polynomial Abstraction for Verification of Sequentially Implemented Combinational Circuits. - Tarvo Raudvere; Ashish Kumar Singh; Ingo Sander; Axel Jantsch (DATE, 2004)

System level verification of digital signal processing applications based on the polynomial abstraction technique. - Tarvo Raudvere; Ashish Kumar Singh; Ingo Sander; Axel Jantsch (ICCAD, 2005)

Synchronization after design refinements with sensitive delay elements. - Tarvo Raudvere; Ingo Sander; Axel Jantsch (CODES+ISSS, 2007)

A synchronization algorithm for local temporal refinements in perfectly synchronous models with nested feedback loops. - Tarvo Raudvere; Ingo Sander; Axel Jantsch (ACM Great Lakes Symposium on VLSI, 2007)

System Level Techniques for Verification and Synchronization after Local Design Refinements. - Tarvo Raudvere (2007)

Application and Verification of Local Nonsemantic-Preserving Transformations in System Design. - Tarvo Raudvere; Ingo Sander; Axel Jantsch (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)