Measurement of digital noise in mixed-signal integrated circuits. - Keiko Makie-Fukuda; Takafumi Kikuchi; Tatsuji Matsuura; Masao Hotta (IEEE J. Solid State Circuits, 1995)

Voltage-comparator-based measurement of equivalently sampled substrate noise waveforms in mixed-signal integrated circuits. - Keiko Makie-Fukuda; Takanobu Anbo; Toshiro Tsukada; Tatsuji Matsuura; Masao Hotta (IEEE J. Solid State Circuits, 1996)

Correction to "Voltage-Comparator-Based Measurement of Equivalentiy Samlpled Substrate Noise Wavefor. - Keiko Makie-Fukuda; Takanobu Anbo; Toshiro Tsukada; Tatsuji Matsuura; Masao Hotta (IEEE J. Solid State Circuits, 1996)

Error suppressing encode logic of FCDL in a 6-b flash A/D converter. - Koichi Ono; Tatsuji Matsuura; Eiki Imaizumi; Hisashi Okazawa; Ryuushi Shimokawa (IEEE J. Solid State Circuits, 1997)

A 240-Mbps, 1-W CMOS EPRML read-channel LSI chip using an interleaved subranging pipeline A/D converter. - Tatsuji Matsuura; Takashi Nara; Tatsuya Komatsu; Eiki Imaizumi; Toshihiro Matsutsuru; Ryutaro Horita; Haruto Katsu; Shintaro Suzumura; Kazuo Sato (IEEE J. Solid State Circuits, 1998)

A Novel False Lock Detection Technique for a Wide Frequency Range Delay-Locked Loop. - Yasutoshi Aibara; Eiki Imaizumi; Hiroaki Takagishi; Tatsuji Matsuura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

Key Technologies for Miniaturization and Power Reduction of Analog-to-Digital Converters for Video Use. - Masao Hotta; Tatsuji Matsuura (IEICE Trans. Electron., 2006)

Complex Bandpass DeltaSigmaAD Modulator Architecture without I, Q-Path Crossing Layout. - Hao San; Akira Hayakawa; Yoshitaka Jingu; Hiroki Wada; Hiroyuki Hagiwara; Kazuyuki Kobayashi; Haruo Kobayashi 001; Tatsuji Matsuura; Kouichi Yahagi; Junya Kudoh; Hideo Nakane; Masao Hotta; et al. (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

A 63-mA 112/94-dB DR IF bandpass ΔΣ modulator with direct feed-forward and double sampling. - Takaya Yamamoto; Masumi Kasahara; Tatsuji Matsuura (CICC, 2007)

1-GHz Input bandwidth 6-bit under-sampling A/D converter for UWB-IR receiver. - Tatsuo Nakagawa; Tatsuji Matsuura; Eiki Imaizumi; Junya Kudoh; Goichi Ono; Masayuki Miyazaki; Akira Maeki; Yuji Ogata; Shinsuke Kobayashi; Noboru Koshizuka; Ken Sakamura (ESSCIRC, 2007)

ΔΣ ADCs and Converter Techniques. - Zhongyuan Chang; Tatsuji Matsuura (ISSCC, 2007)

A Second-Order Multibit Complex Bandpass DeltaSigmaAD Modulator with I, Q Dynamic Matching and DWA Algorithm. - Hao San; Yoshitaka Jingu; Hiroki Wada; Hiroyuki Hagiwara; Akira Hayakawa; Haruo Kobayashi 001; Tatsuji Matsuura; Kouichi Yahagi; Junya Kudoh; Hideo Nakane; Masao Hotta; Toshiro Tsukada; et al. (IEICE Trans. Electron., 2007)

A 63 mA 112/94 dB DR IF Bandpass ΔΣ Modulator With Direct Feed-Forward Compensation and Double Sampling. - Takaya Yamamoto; Masumi Kasahara; Tatsuji Matsuura (IEEE J. Solid State Circuits, 2008)

1-GHz Input Bandwidth Under-Sampling A/D Converter with Dynamic Current Reduction Comparator for UWB-IR Receiver. - Tatsuo Nakagawa; Tatsuji Matsuura; Eiki Imaizumi; Junya Kudoh; Goichi Ono; Masayuki Miyazaki (IEICE Trans. Electron., 2009)

SAR ADC that is configurable to optimize yield. - Tomohiko Ogawa; Haruo Kobayashi 001; Yohei Tan; Satoshi Ito; Satoshi Uemori; Nobukazu Takai; Kiichi Niitsu; Takahiro J. Yamaguchi; Tatsuji Matsuura; Nobuyoshi Ishikawa (APCCAS, 2010)

Non-binary SAR ADC with digital error correction for low power applications. - Tomohiko Ogawa; Tatsuji Matsuura; Haruo Kobayashi 001; Nobukazu Takai; Masao Hotta; Hao San; Akira Abe; Katsuyoshi Yagi; Toshihiko Mori (APCCAS, 2010)

Background calibration algorithm for pipelined ADC with open-loop residue amplifier using split ADC structure. - Takuya Yagi; Kunihiko Usui; Tatsuji Matsuura; Satoshi Uemori; Yohei Tan; Satoshi Ito; Haruo Kobayashi 001 (APCCAS, 2010)

SAR ADC Algorithm with Redundancy and Digital Error Correction. - Tomohiko Ogawa; Haruo Kobayashi 001; Yosuke Takahashi; Nobukazu Takai; Masao Hotta; Hao San; Tatsuji Matsuura; Akira Abe; Katsuyoshi Yagi; Toshihiko Mori (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

Background Self-Calibration Algorithm for Pipelined ADC Using Split ADC Scheme. - Takuya Yagi; Kunihiko Usui; Tatsuji Matsuura; Satoshi Uemori; Satoshi Ito; Yohei Tan; Haruo Kobayashi 001 (IEICE Trans. Electron., 2011)

Multi-bit sigma-delta TDC architecture with self-calibration. - Satoshi Uemori; Masamichi Ishii; Haruo Kobayashi 001; Yuta Doi; Osamu Kobayashi; Tatsuji Matsuura; Kiichi Niitsu; Yuta Arakawa; Daiki Hirabayashi; Yuji Yano; Tatsuhiro Gake; Nobukazu Takai; et al. (APCCAS, 2012)

Multi-bit Sigma-Delta TDC Architecture with Improved Linearity. - Satoshi Uemori; Masamichi Ishii; Haruo Kobayashi 001; Daiki Hirabayashi; Yuta Arakawa; Yuta Doi; Osamu Kobayashi; Tatsuji Matsuura; Kiichi Niitsu; Yuji Yano; Tatsuhiro Gake; Takahiro J. Yamaguchi; et al. (J. Electron. Test., 2013)

An area-efficient 12-bit 1.25MS/s radix-value self-estimated non-binary ADC with relaxed requirements on analog components. - Hao San; Rompei Sugawara; Masao Hotta; Tatsuji Matsuura; Kazuyuki Aihara (CICC, 2014)

A Fully Integrated SAR ADC Using Digital Correction Technique for Triple-Mode Mobile Transceiver. - Hideo Nakane; Ryuichi Ujiie; Takashi Oshima; Takaya Yamamoto; Keisuke Kimura; Yuichi Okuda; Kosuke Tsuiji; Tatsuji Matsuura (IEEE J. Solid State Circuits, 2014)

A 10-bit 10Ms/s pipeline cyclic ADC based on β-expansion. - Yuta Mishima; Toshiki Yamada; Asato Uchiyama; Tatsuji Matsuura; Hao San; Masao Hotta (ISPACS, 2015)

A Replica-Amp Gain Enhancement Technique for an Operational Amplifier with Low Mismatch Sensitivity and High Voltage Swing. - Junya Matsuno; Masanori Furuta; Tetsuro Itakura; Tatsuji Matsuura; Akira Hyogo (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

Non-binary cyclic ADC with correlated level shifting technique. - Hiroyuki Tsuchiya; Asato Uchiyama; Yuta Misima; Yuki Watanabe; Tatsuji Matsuura; Hao San; Masao Hotta (ASP-DAC, 2017)

A 14bit 80kSPS non-binary cyclic ADC without high accuracy analog components. - Yuki Watanabe; Hayato Narita; Hiroyuki Tsuchiya; Tatsuji Matsuura; Hao San; Masao Hotta (ASP-DAC, 2017)

A 12-Bit 3.3MS/S pipeline cyclic ADC with correlated level shifting technique. - Koken Chin; Yuta Mishima; Yuki Watanabe; Hiroyuki Tsuchiya; Hao San; Tatsuji Matsuura; Masao Hotta (ISPACS, 2017)

The design of a 14-bit 400kSPS non-binary pipeline cyclic ADC. - Hiroyuki Tsuchiya; Yuki Watanabe; Koken Chin; Hao San; Tatsuji Matsuura; Masao Hotta (ISPACS, 2017)

Experimental results of reconfigurable non-binary cyclic ADC. - Yuki Watanabe; Koken Chin; Hiroyuki Tsuchiya; Hao San; Tatsuji Matsuura; Masao Hotta (ISPACS, 2017)

Non-binary cyclic and binary SAR hybrid ADC. - Kota Inoue; Tatsuji Matsuura; Akira Hyogo; Hao San (MIXDES, 2017)

Integrated CMOS ADC - Tutorial review on recent hybrid SAR-ADCs. - Tatsuji Matsuura (MIXDES, 2017)

A 12-bit 1.25MS/s Area-Efficient Radix-Value Self-Estimated Non-Binary Cyclic ADC with Relaxed Requirements on Analog Components. - Hao San; Rompei Sugawara; Masao Hotta; Tatsuji Matsuura; Kazuyuki Aihara (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

A Novel C-2αC Ladder Based Non-binary DAC for SAR-ADC Using Unit Capacitors. - Satoshi Sekine; Tatsuji Matsuura; Ryo Kishida; Akira Hyogo (ISPACS, 2018)

Investigation of Hybrid ADC Combined with First-order Feedforward Incremental and SAR ADCs. - Yuichiro Kobayashi; Tatsuji Matsuura; Ryo Kishida; Akira Hyogo (ISPACS, 2019)

Duty Ratio and Capacitance Analysis of AC/DC Converter without Current Control Circuit. - Yuki Tanaka; Tatsuji Matsuura; Ryo Kishida; Akira Hyogo (ISPACS, 2019)

Examination of Incremental ADC with SAR ADC to Reduce Conversion Time with High Accuracy. - Yuichiro Unno; Tatsuji Matsuura; Ryo Kishida; Akira Hyogo (ISPACS, 2019)

A 0.8V 14bit 62.5kSPS non-binary cyclic ADC using SOTB CMOS technology. - Shuichiro Yamada; Toshiki Ohtsu; Minami Sasaki; Hao San; Tatsuji Matsuura; Masao Hotta (ISPACS, 2019)

A 0.8V 14bit 294kSPS non-binary cyclic ADC in 65nm SOTB CMOS technology. - Eiki Kayama; Kenta Mori; Taichi Maebou; Yuanchi Chen; Hao San; Tatsuji Matsuura; Masao Hotta (ISPACS, 2021)

A 0.7V 14bit Hybrid ADC in 65nm SOTB CMOS. - Taichi Maebou; Yuanchi Chen; Eiki Kayama; Kenta Mori; Hao San; Tatsuji Matsuura; Masao Hotta (ISPACS, 2021)

A Low-voltage Non-binary Cyclic ADC using Fully Differential Ring Amplifier. - Kenta Mori; Eiki Kayama; Taichi Maebou; Yuanchi Chen; Hao San; Tatsuji Matsuura; Masao Hotta (ISPACS, 2021)

Digital Calibration Algorithm of Conversion Error Influenced by Parasitic Capacitance in C-C SAR-ADC Based on γ-Estimation. - Satoshi Sekine; Tatsuji Matsuura; Ryo Kishida; Akira Hyogo (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021)

Thermal Noise Analysis of Ring Amplifier in Cyclic Analog-to-Digital Converter. - Eiki Kayama; Kenta Mori; Taichi Maebou; Yuanchi Chen; Hao San; Tatsuji Matsuura; Masao Hotta (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2023)