2-V/100-ns 1T/1C nonvolatile ferroelectric memory architecture with bitline-driven read scheme and nonrelaxation reference cell. - Hiroshige Hirano; Toshiyuki Honda; Nobuyuki Moriwaki; Tetsuji Nakakuma; Atsuo Inoue; George Nakane; Shigeo Chaya; Tatsumi Sumi (IEEE J. Solid State Circuits, 1997)