1.3- mu m CMOS/bipolar standard cell library for VLSI computers. - Takashi Hotta; Kouzaburou Kurita; Hideo Maejima; Masahiro Iwamura; Shigeya Tanaka; Tadaaki Bandoh; Tatsumi Yamauchi; Atsuo Hotta (IEEE J. Solid State Circuits, 1988)

A 6-ns 256-kb BiCMOS TTL SRAM. - Takashi Akioka; Atsushi Hiraishi; Tatsumi Yamauchi; Yuji Yokoyama; Shigeru Takahashi; Masahiro Iwamura; Yutaka Kobayashi; Akira Ide; Nobuyuki Gotou; Kazunori Onozawa; Hideaki Uchida (IEEE J. Solid State Circuits, 1991)

3.3-V BiCMOS circuit techniques for a 120-MHz RISC microprocessor. - Fumio Murabayashi; Takashi Hotta; Shigeya Tanaka; Tatsumi Yamauchi; Hiromichi Yamada; Tetsuo Nakano; Yutaka Kobayashi; Tadaaki Bandoh (IEEE J. Solid State Circuits, 1994)

A 13.3ns double-precision floating-point ALU and multiplier. - Hiromichi Yamada; Takashi Hotta; Takahiro Nishiyama; Fumio Murabayashi; Tatsumi Yamauchi; Hideo Sawamoto (ICCD, 1995)

2.5 V CMOS circuit techniques for a 200 MHz superscalar RISC processor. - Fumio Murabayashi; Tatsumi Yamauchi; Hiromichi Yamada; Takahiro Nishiyama; Kotaro Shimamura; Shigeya Tanaka; Takashi Hotta; Teruhisa Shimizu; Hideo Sawamoto (IEEE J. Solid State Circuits, 1996)