A 55-ns 16-Mb DRAM with built-in self-test function using microprogram ROM. - Toshio Takeshima; Masahide Takada; Hiroki Koike; Hiroshi Watanabe; Shigeru Koshimaru; Kenjiro Mitake; Wataru Kikuchi; Takaho Tanigawa; Tatsunori Murotani; Kenji Noda; Kazuhiro Tasaka; Koji Yamanaka; et al. (IEEE J. Solid State Circuits, 1990)

A 30-ns 64-Mb DRAM with built-in self-test and self-repair function. - Akira Tanabe; Toshio Takeshima; Hiroki Koike; Yoshiharu Aimoto; Masahide Takada; Toshiyuki Ishijima; Naoki Kasai; Hiromitsu Hada; Kentaro Shibahara; Takemitsu Kunio; Takaho Tanigawa; Takanori Saeki; et al. (IEEE J. Solid State Circuits, 1992)

A 30-ns 256-Mb DRAM with a multidivided array structure. - Tadahiko Sugibayashi; Toshio Takeshima; Isao Naritake; Tatsuya Matano; Hiroshi Takada; Yoshiharu Aimoto; Koichiro Furuta; Mamoru Fujita; Takanori Saeki; Hiroshi Sugawara; Tatsunori Murotani; Naoki Kasai; et al. (IEEE J. Solid State Circuits, 1993)

A 1-Gb DRAM for file applications. - Tadahiko Sugibayashi; Isao Naritake; Satoshi Utsugi; Kentaro Shibahara; Ryuichi Oikawa; Hidemitsu Mori; Shouichi Iwao; Tatsunori Murotani; Kuniaki Koyama; Shinichi Fukuzawa; Toshiro Itani; Kunihiko Kasama; et al. (IEEE J. Solid State Circuits, 1995)

A four-level storage 4-Gb DRAM. - Takashi Okuda; Tatsunori Murotani (IEEE J. Solid State Circuits, 1997)

A 12-ns 8-Mbyte DRAM secondary cache for a 64-bit microprocessor. - Takashi Okuda; Isao Naritake; Tadahiko Sugibayashi; Yuji Nakajima; Tatsunori Murotani (IEEE J. Solid State Circuits, 2000)