Static-Hazard-Free T-Gate for Ternary Memory Element and Its Application to Ternary Counters. - Tatsuo Higuchi 001; Michitaka Kameyama (IEEE Trans. Computers, 1977)

Synthesis of Multiple-Valued Logic Networks Based on Tree-Type Universal Logic Module. - Michitaka Kameyama; Tatsuo Higuchi 001 (IEEE Trans. Computers, 1977)

Special-purpose ternary computer for digital filtering. - Tatsuo Higuchi 001; Hisamitsu Hoshi (MVL, 1978)

A state-space approach for elimination of limit cycles in digital filters with arbitrary structures. - Tatsuo Higuchi 001; Hiroski Takeo (ICASSP, 1979)

A sufficient condition for absence of overflow oscillations in arbitrary digital filters based on the element equations. - Masayuki Kawamata; Tatsuo Higuchi 001 (ICASSP, 1980)

Another discrete Fourier transform computation with small multiplications via the Walsh transform. - Yoshiaki Tadokoro; Tatsuo Higuchi 001 (ICASSP, 1981)

A unified approach to the optimal synthesis of fixed-point state-space digital filters. - Masayuki Kawamata; Tatsuo Higuchi 001 (IEEE Trans. Acoust. Speech Signal Process., 1985)

Synthesis of minimum sensitivity structures in linear systems using controllability and observability measures. - Masami Iwatsuki; Masayuki Kawamata; Tatsuo Higuchi 001 (ICASSP, 1986)

A unified study on the roundoff noise in 2-D state space digital filters. - Tao Lin; Masayuki Kawamata; Tatsuo Higuchi 001 (ICASSP, 1986)

A unified design method of state-space digital filters using system balancing concept. - Qiangfu Zhao; Masayuki Kawamata; Tatsuo Higuchi 001 (ICASSP, 1986)

Design of lsi-oriented digital signal processing system Based on Pulse-Train Residue Arithmetic Circuits. - Nobuhiro Tomabechi; Michitaka Kameyama; Tatsuo Higuchi 001 (Syst. Comput. Jpn., 1986)

Design of low-power quaternary CMOS logic circuits. - Chotei Zukeran; Chushin Afuso; Michitaka Kameyama; Tatsuo Higuchi 001 (Syst. Comput. Jpn., 1986)

Design and implementation of an nmos image processor based on quaternary logic. - Takahiro Hanyu; Michitaka Kameyama; Tatsuo Higuchi 001 (Syst. Comput. Jpn., 1987)

Design of VLSI-oriented radix-4 signed-digit arithmetic circuits using multiple-valued logic. - Shoji Kawahito; Michitaka Kameyama; Tatsuo Higuchi 001 (Syst. Comput. Jpn., 1987)

Design of micropower CMOS quaternary memory circuits. - Chotei Zukeran; Chushin Afuso; Michitaka Kameyama; Tatsuo Higuchi 001 (Syst. Comput. Jpn., 1987)

A Multiplier Chip with Multiple-Valued Bidirectional Current-Mode Logic Circuits. - Michitaka Kameyama; Shoji Kawahito; Tatsuo Higuchi 001 (Computer, 1988)

Design of a time-optimal digital control system for a dc-servomotor with amplitude limitation. - Xi Yue Huang; Michitaka Kameyama; Tatsuo Higuchi 001 (Syst. Comput. Jpn., 1988)

Design of a Fault-Tolerant System Based on Knowledge-Engineering Approach and Its Application to a Digital Control System. - Michitaka Kameyama; Li Zheng; Tatsuo Higuchi 001 (Syst. Comput. Jpn., 1988)

A 32*32-bit multiplier using multiple-valued MOS current-mode circuits. - Shoji Kawahito; Michitaka Kameyama; Tatsuo Higuchi 001; Haruyasu Yamada (IEEE J. Solid State Circuits, 1988)

Implementation of a high performance LSI for inverse kinematics computation. - Michitaka Kameyama; Takao Matsumoto; Hideki Egami; Tatsuo Higuchi 001 (ICRA, 1989)

VLSI Computer for Robotics. - Michitaka Kameyama; Tatsuo Higuchi 001 (J. Robotics Mechatronics, 1989)

Design of a Multiple-Valued Associative Memory. - Takahiro Hanyu; Tatsuo Higuchi 001 (Syst. Comput. Jpn., 1989)

Bi-directional current-mode basic circuits for the multilevel signed-digit arithmetic and their evaluation. - Michitaka Kameyama; Shoji Kawahito; Tatsuo Higuchi 001 (Syst. Comput. Jpn., 1989)

High-density quaternary logic array chip for knowledge information processing systems. - Takahiro Hanyu; Tatsuo Higuchi 001 (IEEE J. Solid State Circuits, 1989)

Highly parallel residue arithmetic chip based on multiple-valued bidirectional current-mode logic. - Michitaka Kameyama; Tsutomu Sekibe; Tatsuo Higuchi 001 (IEEE J. Solid State Circuits, 1989)

Design of a High-Density Multiple-Valued Content-Addressable Memory Based on Floating-Gate MOS Devices. - Takahiro Hanyu; Tatsuo Higuchi 001 (ISMVL, 1990)

Modular Design of Multiple-Valued Arithmetic VLSI System Using Signed-Digit Number System. - Michitaka Kameyama; Masahiro Nomura; Tatsuo Higuchi 001 (ISMVL, 1990)

High-Performance LSI for Kinematics Computation. - Tatsuo Higuchi 001 (J. Robotics Mechatronics, 1990)

Robot Electronics System. - Tatsuo Higuchi 001; Michitaka Kameyama (J. Robotics Mechatronics, 1990)

Design of a Parallel Collision Detection Check VLSI Processor for Robot Manipulator. - Tadao Amada; Michitaka Kameyama; Tatsuo Higuchi 001 (J. Robotics Mechatronics, 1990)

Design of a Matrix Multiply-Addition VLSI Processor for Robot control. - Somchai Kittichaikoonkit; Michitaka Kameyama; Tatsuo Higuchi 001 (J. Robotics Mechatronics, 1990)

Design of a Highly Parallel Ultrahigher-Valued Logic Network Based on a Bio-Device Model. - Michitaka Kameyama; Takafumi Aoki; Tatsuo Higuchi 001 (Syst. Comput. Jpn., 1990)

Design of an RSA Encryption Processor Based on Signed-Digit Multivalued Arithmetic Circuits. - Michitaka Kameyama; Shugang Wei; Tatsuo Higuchi 001 (Syst. Comput. Jpn., 1990)

Design of a fault-tolerant arithmetic circuit based on distributed coding and its evaluation. - Takeshi Kasuga; Michitaka Kameyama; Tatsuo Higuchi 001 (Syst. Comput. Jpn., 1990)

Multiple-valued radix-2 signed-digit arithmetic circuits for high-performance VLSI systems. - Shoji Kawahito; Michitaka Kameyama; Tatsuo Higuchi 001 (IEEE J. Solid State Circuits, 1990)

High-Performance VLSI Processor for Robot Inverse Dynamics Computation. - Somchai Kittichaikoonkit; Michitaka Kameyama; Tatsuo Higuchi 001 (ICCD, 1991)

Design of Interconnection-Free Biomolecular Computing System. - Takafumi Aoki; Michitaka Kameyama; Tatsuo Higuchi 001 (ISMVL, 1991)

A Floating-Gate-MOS-Based Multiple-Valued Associative Memory. - Takahiro Hanyu; Tatsuo Higuchi 001 (ISMVL, 1991)

A Multiple-Valued Logic Artay VLSI Based on Two-Transistor Delta Literal Circuit and Its Application to Real-Time Reasoning Systems. - Takahiro Hanyu; Yasushi Kojima; Tatsuo Higuchi 001 (ISMVL, 1991)

Design of a Set Logic Network Based on Frequency Multiplexing and Its Applications to Image Processing. - Yasushi Yuminaka; Takafumi Aoki; Tatsuo Higuchi 001 (ISMVL, 1991)

Design of a robust fault-tolerant multiplier. - Takeshi Kasuga; Michitaka Kameyama; Tatsuo Higuchi 001 (Syst. Comput. Jpn., 1991)

Performance evaluation of a multivalued rsa encryption vlsi. - Shugang Wei; Michitaka Kameyama; Tatsuo Higuchi 001 (Syst. Comput. Jpn., 1991)

Design of a Multiple-Valued Rule-Programmable Matching VLSI Chip for Real-Time Rule-Based Systems. - Takahiro Hanyu; Kouichi Takeda; Tatsuo Higuchi 001 (ISMVL, 1992)

Residue Arithmetic Based Multiple-Valued VLSI Image Processor. - Makoto Honda; Michitaka Kameyama; Tatsuo Higuchi 001 (ISMVL, 1992)

Set-Valued Logic Networks Based on Optical Wavelength Multiplexing. - Shuichi Maeda; Takafumi Aoki; Tatsuo Higuchi 001 (ISMVL, 1992)

Design of a Multiple-Valued VLSI Processor for Digital Control. - Katsuhiko Shimabukuro; Michitaka Kameyama; Tatsuo Higuchi 001 (ISMVL, 1992)

Code Assignment Algorithm for Highly Parallel Multiple-Valued Combinatorial Circuits. - Saneaki Tamaki; Michitaka Kameyama; Tatsuo Higuchi 001 (ISMVL, 1992)

Interconnection-Free Biomolecular Computing. - Takafumi Aoki; Michitaka Kameyama; Tatsuo Higuchi 001 (Computer, 1992)

Design of an ultrahigher-valued biocomputing system based on set-valued logic networks. - Takafumi Aoki; Michitaka Kameyama; Tatsuo Higuchi 001 (Syst. Comput. Jpn., 1992)

Highly parallel collision detection processor for intelligent robots. - Michitaka Kameyama; Tadao Amada; Tatsuo Higuchi 001 (IEEE J. Solid State Circuits, 1992)

Design of Fine Grain VLSI Array Processor for Real-time 2-D Digital Filtering. - Yasushi Iwata; Masayuki Kawamata; Tatsuo Higuchi 001 (ISCAS, 1993)

Realization of lattice-form separable-denominator 2D adaptive filters. - Masayuki Kawamata; Eiichiro Kawakami; Tatsuo Higuchi 001 (ISCAS, 1993)

Impact of Interconnection-Free Biomolecular Computing. - Takafumi Aoki; Tatsuo Higuchi 001 (ISMVL, 1993)

A Multiple-Valued Content-Addressable Memory Using Logic-Value Conversion and Threshold Functions. - Satoshi Aragaki; Takahiro Hanyu; Tatsuo Higuchi 001 (ISMVL, 1993)

Design of Set-Valued Logic Networks for Wave-Parallel Computing. - Yasushi Yuminaka; Takafumi Aoki; Tatsuo Higuchi 001 (ISMVL, 1993)

Design of 2-d Digital filters Based on the Optimal Decomposition of Magnitude Specifications. - Tian-Bo Deng; Masayuki Kawamata; Tatsuo Higuchi 001 (J. Circuits Syst. Comput., 1993)

Multi-valued current-mode parallel multiplier based on redundant positive-digit number representations. - Shoui Kaqahito; Makoto Ishida; Tetsuro Nakamura; Kentaro Mizuno; Michitaka Kameyama; Tatsuo Higuchi 001 (Syst. Comput. Jpn., 1993)

Optimal Design Method of 2-D IIR Digital Filters Based on a Simple Genetic Algorithm. - Masayuki Kawamata; Jun Imakubo; Tatsuo Higuchi 001 (ICIP (1), 1994)

Multi-resolution Tree Search for Iterated Transformation Theory-Based Coding. - Masayuki Kawamata; Masaki Nagahisa; Tatsuo Higuchi 001 (ICIP (3), 1994)

Design of Multiplex Interconnection Networks for Massively Parallel Computing Systems. - Takashi Takimoto; Takafumi Aoki; Tatsuo Higuchi 001 (ISMVL, 1994)

Design of Multiwave Computing Circuits Based on a Modle of Integrated Opto-Electronic Devices. - Yukio Watanabe; Takafumi Aoki; Tatsuo Higuchi 001 (ISMVL, 1994)

Design of Wave-Parallel Computing Circuits for Densely Connected Architectures. - Yasushi Yuminaka; Takafumi Aoki; Tatsuo Higuchi 001 (ISMVL, 1994)

Design of an Intelligent Fault-Tolerant System for Real-World Applications. - Shigeki Abe; Michitaka Kameyama; Tatsuo Higuchi 001 (J. Robotics Mechatronics, 1994)

Coordinate Transformation VLSI Processor for Redundant Manipulator Control. - Yoshichika Fujioka; Michitaka Kameyama; Tatsuo Higuchi 001 (J. Robotics Mechatronics, 1994)

High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits. - Shoji Kawahito; Makoto Ishida; Tetsuro Nakamura; Michitaka Kameyama; Tatsuo Higuchi 001 (IEEE Trans. Computers, 1994)

An Evolutionary Algorithm for Solving Multi-Individual-Multi-Task Problems. - Qiangfu Zhao; Tatsuo Higuchi 001 (BIES, 1995)

Multiwave Interconnection Networks for MCM-based Parallel Processing. - Shinichi Shionoya; Takafumi Aoki; Tatsuo Higuchi 001 (Euro-Par, 1995)

Design of 2-D state-space digital filters with powers-of-two coefficients based on a genetic algorithm. - Young-Ho Lee; Masayuki Kawamata; Tatsuo Higuchi 001 (ICIP, 1995)

Redundant Complex Number Systems. - Yuji Ohi; Takafumi Aoki; Tatsuo Higuchi 001 (ISMVL, 1995)

Wire-Free Computing Circuits Using Optical Wave-Casting. - S. Sakurai; Takafumi Aoki; Tatsuo Higuchi 001 (ISMVL, 1995)

Individual Evolutionary Algorithm and its Application to Learning of Nearest Neighbor Based MLP. - Qiangfu Zhao; Tatsuo Higuchi 001 (IWANN, 1995)

GA-based design of multiplierless 2-D state-space digital filters with very small roundoff noise. - Young-Ho Lee; Masayuki Kawamata; Tatsuo Higuchi 001 (ICASSP, 1996)

Wave-Parallel Computing Technique for Neural Networks Based on Amplitude-Modulated Waves. - Yasushi Yuminaka; Yoshisato Sasaki; Takafumi Aoki; Tatsuo Higuchi 001 (ISMVL, 1996)

Efficient learning of NN-MLP based on individual evolutionary algorithm. - Qiangfu Zhao; Tatsuo Higuchi 001 (Neurocomputing, 1996)

Minimization of nearest neighbor classifiers based on individual evolutionary algorithm. - Qiangfu Zhao; Tatsuo Higuchi 001 (Pattern Recognit. Lett., 1996)

Author's Reply. - Shoji Kawahito; Makoto Ishida; Tasuro Nakamura; Michitaka Kameyama; Tatsuo Higuchi 001 (IEEE Trans. Computers, 1996)

Evolutionary learning of nearest-neighbor MLP. - Qiangfu Zhao; Tatsuo Higuchi 001 (IEEE Trans. Neural Networks, 1996)

Real/Complex Reconfigurable Arithmetic Using Redundant Complex Number Systems. - Takafumi Aoki; Hiroaki Amada; Tatsuo Higuchi 001 (IEEE Symposium on Computer Arithmetic, 1997)

Enzyme Transistor Circuits for Biomolecular Computing. - Masahiko Hiratsuka; Takafumi Aoki; Tatsuo Higuchi 001 (ISMVL, 1997)

Communication network protocol for real-time distributed control and its LSI implementation. - Koji Kobayashi; Michitaka Kameyama; Tatsuo Higuchi 001 (IEEE Trans. Ind. Electron., 1997)

Set-Valued Logic Circuits for Next Generation VLSI Architectures. - Takafumi Aoki; Tatsuo Higuchi 001 (ISMVL, 1998)

Wave-Parallel Computing Systems using Multiple-Valued Pseudo-Orthogonal Sequences. - Yasushi Yuminaka; Yoshisat Sasaki; Takafumi Aoki; Tatsuo Higuchi 001 (ISMVL, 1998)

Redundant Complex Arithmetic and Its Application to Complex Multiplier Design. - Takafumi Aoki; Ken-ichi Hoshi; Tatsuo Higuchi 001 (ISMVL, 1999)

High-Radix Parallel VLSI Dividers without Using Quotient Digit Selection Tables. - Takafumi Aoki; Kimihiko Nakazawa; Tatsuo Higuchi 001 (ISMVL, 2000)

An Efficient Data Transmission Technique for VLSI Systems Based on Multiple-Valued Code-Division Multiple Access. - Yasushi Yuminaka; Osamu Katoh; Yoshisat Sasaki; Takafumi Aoki; Tatsuo Higuchi 001 (ISMVL, 2000)

Distributed evolutionary design of constant-coefficient multipliers. - Dingjun Chen; Takafumi Aoki; Naofumi Homma; Tatsuo Higuchi 001 (ICECS, 2001)

Evolutionary graph generation system with transmigration capability for arithmetic circuit design. - Naofumi Homma; Takafumi Aoki; Tatsuo Higuchi 001 (ISCAS (5), 2001)

A Model of Reaction-Diffusion Cellular Automata for Massively Parallel Molecular Computing. - Masahiko Hiratsuka; Takafumi Aoki; Tatsuo Higuchi 001 (ISMVL, 2001)

Synthesis of Multiple-Valued Arithmetic Circuits Using Evolutionary Graph Generation. - Masanori Natsui; Takafumi Aoki; Tatsuo Higuchi 001 (ISMVL, 2001)

An LVQ-based technique for human motion segmentation. - Mochamad Hariadi; Akio Harada; Takafumi Aoki; Tatsuo Higuchi 001 (APCCAS (2), 2002)

Graph-based individual representation for evolutionary synthesis of arithmetic circuits. - Naofumi Homma; Takafumi Aoki; Tatsuo Higuchi 001 (IEEE Congress on Evolutionary Computation, 2002)

Pixel-wise human motion segmentation using learning vector quantization. - Mochamad Hariadi; Akio Harada; Takafumi Aoki; Tatsuo Higuchi 001 (ICARCV, 2002)

Parallel Evolutionary Graph Synthesis on a PC Cluster and Its Application to Multiple-Valued Circuit Synthesis. - Masanori Natsui; Takafumi Aoki; Tatsuo Higuchi 001 (ISMVL, 2002)

Multiple-Valued Data Recovery Techniques for Band-Limited Channels in VLSI. - Yasushi Yuminaka; Tatsuya Morishita; Takafumi Aoki; Tatsuo Higuchi 001 (ISMVL, 2002)

Evolutionary Graph Generation System and Its Application to Bit-Serial Arithmetic Circuit Synthesis. - Makoto Motegi; Naofumi Homma; Takafumi Aoki; Tatsuo Higuchi 001 (PPSN, 2002)

Parallel Evolutionary Design of Constant-Coefficient Multipliers. - Dingjun Chen; Takafumi Aoki; Naofumi Homma; Tatsuo Higuchi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

Parallel Evolutionary Graph Generation with Terminal-Color Constraint and Its Application to Current-Mode Logic Circuit Design. - Masanori Natsui; Takafumi Aoki; Tatsuo Higuchi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

Graph-based evolutionary design of arithmetic circuits. - Dingjun Chen; Takafumi Aoki; Naofumi Homma; Toshiki Terasaki; Tatsuo Higuchi 001 (IEEE Trans. Evol. Comput., 2002)

VLSI circuit design using an object-oriented framework of evolutionary graph generation system. - Naofumi Homma; Masanori Natsui; Takafumi Aoki; Tatsuo Higuchi 001 (IEEE Congress on Evolutionary Computation, 2003)

A framework of evolutionary graph generation system and its application to circuit synthesis. - Naofumi Homma; Takafumi Aoki; Makoto Motegi; Tatsuo Higuchi 001 (ISCAS (5), 2003)

Design of a digital reaction-diffusion system for restoring blurred fingerprint images. - Koichi Ito 001; Takafumi Aoki; Tatsuo Higuchi 001 (ISCAS (4), 2003)

A Field-Programmable Digital Filter Chip Using Multiple-Valued Current-Mode Logic. - Katsuhiko Degawa; Takafumi Aoki; Tatsuo Higuchi 001 (ISMVL, 2003)

Counter Tree Diagrams for Design and Analysis of Fast Addition Algorithms. - Jun Sakiyama; Takafumi Aoki; Tatsuo Higuchi 001 (ISMVL, 2003)

Evolutionary Synthesis of Arithmetic Circuit Structures. - Takafumi Aoki; Naofumi Homma; Tatsuo Higuchi 001 (Artif. Intell. Rev., 2003)

Design of a Field-Programmable Digital Filter Chip Using Multiple-Valued Current-Mode Logic. - Katsuhiko Degawa; Takafumi Aoki; Tatsuo Higuchi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

Fingerprint Restoration Using Digital Reaction-Diffusion System and Its Evaluation. - Koichi Ito 001; Takafumi Aoki; Tatsuo Higuchi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

Counter Tree Diagrams: A Unified Framework for Analyzing Fast Addition Algorithms. - Jun Sakiyama; Naofumi Homma; Takafumi Aoki; Tatsuo Higuchi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

High-Accuracy Subpixel Image Registration Based on Phase-Only Correlation. - Kenji Takita; Takafumi Aoki; Yoshifumi Sasaki; Tatsuo Higuchi 001; Koji Kobayashi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

Counter Tree Diagrams: A Unified Representation of Fast Addition Algorithms. - Jun Sakiyama; Takafumi Aoki; Tatsuo Higuchi 001 (J. Multiple Valued Log. Soft Comput., 2003)

Multiplier Block Synthesis Using Evolutionary Graph Generation. - Naofumi Homma; Takafumi Aoki; Tatsuo Higuchi 001 (Evolvable Hardware, 2004)

A systematic approach for analyzing fast addition algorithms using counter tree diagrams. - Naofumi Homma; Jun Sakiyama; Taihei Wakamatsu; Takafumi Aoki; Tatsuo Higuchi 001 (ISCAS (5), 2004)

A Single-Electron-Transistor Logic Gate Family and Its Application - Part I: Basic Components for Binary, Multiple-Valued and Mixed-Mode Logic. - Katsuhiko Degawa; Takafumi Aoki; Tatsuo Higuchi 001; Hiroshi Inokawa; Yasuo Takahashi (ISMVL, 2004)

A Single-Electron-Transistor Logic Gate Family and Its Application - Part II: Design and Simulation of a 7-3 Parallel Counter with Linear Summation and Multiple-Valued Latch Functions. - Hiroshi Inokawa; Yasuo Takahashi; Katsuhiko Degawa; Takafumi Aoki; Tatsuo Higuchi 001 (ISMVL, 2004)

Design and Verification of Parallel Multipliers Using Arithmetic Description Language: ARITH. - Kazuya Ishida; Naofumi Homma; Takafumi Aoki; Tatsuo Higuchi 001 (ISMVL, 2004)

Topology-Oriented Design of Analog Circuits Based on Evolutionary Graph Generation. - Masanori Natsui; Naofumi Homma; Takafumi Aoki; Tatsuo Higuchi 001 (PPSN, 2004)

A fingerprint recognition algorithm using phase-based image matching for low-quality fingerprints. - Koichi Ito 001; Ayumi Morita; Takafumi Aoki; Tatsuo Higuchi 001; Hiroshi Nakajima; Koji Kobayashi (ICIP (2), 2005)

A Two-Bit-per-Cell Content-Addressable Memory Using Single-Electron Transistors. - Katsuhiko Degawa; Takafumi Aoki; Hiroshi Inokawa; Tatsuo Higuchi 001; Yasuo Takahashi (ISMVL, 2005)

A compact cluster computer with embedded CPUs and its application to rapid prototyping of fingerprint verification system. - Yoshifumi Sasaki; Koichi Ito 001; Takafumi Aoki; Tatsuo Higuchi 001 (IEICE Electron. Express, 2005)

Prototype Fabrication of Field-Programmable Digital Filter LSIs Using Multiple-Valued Current-Mode Logic - Device Scaling and Future Prospects. - Katsuhiko Degawa; Takafumi Aoki; Tatsuo Higuchi 001 (J. Multiple Valued Log. Soft Comput., 2005)

Design of Multiple-Valued Logic Circuits Using Graph-Based Evolutionary Synthesis. - Masanori Natsui; Naofumi Homma; Takafumi Aoki; Tatsuo Higuchi 001 (J. Multiple Valued Log. Soft Comput., 2005)

A Fingerprint Recognition Algorithm Combining Phase-Based Image Matching and Feature-Based Matching. - Koichi Ito 001; Ayumi Morita; Takafumi Aoki; Hiroshi Nakajima; Koji Kobayashi; Tatsuo Higuchi 001 (ICB, 2006)

Fast and Robust Fingerprint Identification Algorithm and Its Application to Residential Access Controller. - Hiroshi Nakajima; Koji Kobayashi; Makoto Morikawa; Atsushi Katsumata; Koichi Ito 001; Takafumi Aoki; Tatsuo Higuchi 001 (ICB, 2006)

A Palmprint Recognition Algorithm using Phase-Based Image Matching. - Koichi Ito 001; Takafumi Aoki; Hiroshi Nakajima; Koji Kobayashi; Tatsuo Higuchi 001 (ICIP, 2006)

A High-Density Ternary Content-Addressable Memory Using Single-Electron Transistors. - Katsuhiko Degawa; Takafumi Aoki; Tatsuo Higuchi 001; Hiroshi Inokawa; Katsuhiko Nishiguchi; Yasuo Takahashi (ISMVL, 2006)

Algorithm-level interpretation of fast adder structures in binary and multiple-valued logic. - Naofumi Homma; Takafumi Aoki; Tatsuo Higuchi 001 (ISMVL, 2006)

Systematic Interpretation of Redundant Arithmetic Adders in Binary and Multiple-Valued Logic. - Naofumi Homma; Takafumi Aoki; Tatsuo Higuchi 001 (IEICE Trans. Electron., 2006)

Formal Design of Arithmetic Circuits Based on Arithmetic Description Language. - Naofumi Homma; Yuki Watanabe; Takafumi Aoki; Tatsuo Higuchi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

A Shortest Path Search Algorithm Using an Excitable Digital Reaction-Diffusion System. - Koichi Ito 001; Masahiko Hiratsuka; Takafumi Aoki; Tatsuo Higuchi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

Application of symbolic computer algebra to arithmetic circuit verification. - Yuki Watanabe; Naofumi Homma; Takafumi Aoki; Tatsuo Higuchi 001 (ICCD, 2007)

Algorithm-Level Optimization of Multiple-Valued Arithmetic Circuits Using Counter Tree Diagrams. - Naofumi Homma; Katsuhiko Degawa; Takafumi Aoki; Tatsuo Higuchi 001 (ISMVL, 2007)

Synthesis of current mirrors based on evolutionary graph generation with transmigration capability. - Masanori Natsui; Yoshiaki Tadokoro; Naofumi Homma; Takafumi Aoki; Tatsuo Higuchi 001 (IEICE Electron. Express, 2007)

Design of a Two-Bit-Per-Cell Content-Addressable Memory Using Single-Electron Transistors. - Katsuhiko Degawa; Takafumi Aoki; Tatsuo Higuchi 001; Hiroshi Inokawa; Yasuo Takahashi (J. Multiple Valued Log. Soft Comput., 2007)

Design of Multiple-valued Arithmetic Circuits Using Counter Tree Diagrams. - Naofumi Homma; Katsuhiko Degawa; Takafumi Aoki; Tatsuo Higuchi 001 (J. Multiple Valued Log. Soft Comput., 2007)

Arithmetic module generator with algorithm optimization capability. - Yuki Watanabe; Naofumi Homma; Takafumi Aoki; Tatsuo Higuchi 001 (ISCAS, 2008)

High-Level Design of Multiple-Valued Arithmetic Circuits Based on Arithmetic Description Language. - Yuki Watanabe; Naofumi Homma; Katsuhiko Degawa; Takafumi Aoki; Tatsuo Higuchi 001 (ISMVL, 2008)

A Palmprint Recognition Algorithm Using Phase-Only Correlation. - Koichi Ito 001; Takafumi Aoki; Hiroshi Nakajima; Koji Kobayashi; Tatsuo Higuchi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Arithmetic Circuit Verification Based on Symbolic Computer Algebra. - Yuki Watanabe; Naofumi Homma; Takafumi Aoki; Tatsuo Higuchi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Shortest Path Search Using a Reaction-Diffusion Processor. - Masahiko Hiratsuka; Koichi Ito 001; Takafumi Aoki; Tatsuo Higuchi 001 (Int. J. Unconv. Comput., 2008)

A Systematic Approach for Designing Redundant Arithmetic Adders Based on Counter Tree Diagrams. - Naofumi Homma; Takafumi Aoki; Tatsuo Higuchi 001 (IEEE Trans. Computers, 2008)

Toward Biomolecular Computers Using Reaction-Diffusion Dynamics. - Masahiko Hiratsuka; Koichi Ito 001; Takafumi Aoki; Tatsuo Higuchi 001 (Int. J. Nanotechnol. Mol. Comput., 2009)

Systematic Approach to Designing Multiple-Valued Arithmetic Circuits Based on Arithmetic Description Language. - Naofumi Homma; Yuki Watanabe; Katsuhiko Degawa; Takafumi Aoki; Tatsuo Higuchi 001 (J. Multiple Valued Log. Soft Comput., 2009)

Score-Level Fusion of Phase-Based and Feature-Based Fingerprint Matching Algorithms. - Koichi Ito 001; Ayumi Morita; Takafumi Aoki; Hiroshi Nakajima; Koji Kobayashi; Tatsuo Higuchi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)