A single-chip 802.11a MAC/PHY with a 32-b RISC processor. - Toshio Fujisawa; Jun Hasegawa; Koji Tsuchie; Tatsuo Shiozawa; Tetsuya Fujita; Toshitada Saito; Yasuo Unekawa (IEEE J. Solid State Circuits, 2003)

A 7uW deep-sleep, ultra low-power WLAN baseband LSI for mobile applications. - Daisuke Taki; Tatsuo Shiozawa; Kuniaki Ito; Youichiro Shiba; Kouji Horisaki; Hirotsugu Kajihara; Toshiyuki Yamagishi; Masahiro Sekiya; Akira Yamaga; Tetsuya Fujita; Hiroyuki Hara; Masanori Kuwahara; et al. (COOL Chips, 2011)

An area-efficient, standard-cell based on-chip NMOS and PMOS performance monitor for process variability compensation. - Toshiyuki Yamagishi; Tatsuo Shiozawa; Koji Horisaki; Hiroyuki Hara; Yasuo Unekawa (COOL Chips, 2012)

A Standard-Cell Based On-Chip NMOS and PMOS Performance Monitor for Process Variability Compensation. - Toshiyuki Yamagishi; Tatsuo Shiozawa; Koji Horisaki; Hiroyuki Hara; Yasuo Unekawa (IEICE Trans. Electron., 2013)

Approaching DRAM performance by using microsecond-latency flash memory for small-sized random read accesses: a new access method and its graph applications. - Tomoya Suzuki; Kazuhiro Hiwada; Hirotsugu Kajihara; Shintaro Sano; Shuou Nomura; Tatsuo Shiozawa (Proc. VLDB Endow., 2021)

Implementing and Evaluating E2LSH on Storage. - Yu Nakanishi; Kazuhiro Hiwada; Yosuke Bando; Tomoya Suzuki; Hirotsugu Kajihara; Shintaro Sano; Tatsuro Endo; Tatsuo Shiozawa (EDBT, 2023)

GPU Graph Processing on CXL-Based Microsecond-Latency External Memory. - Shintaro Sano; Yosuke Bando; Kazuhiro Hiwada; Hirotsugu Kajihara; Tomoya Suzuki; Yu Nakanishi; Daisuke Taki; Akiyuki Kaneko; Tatsuo Shiozawa (SC Workshops, 2023)