Delay-Time Modeling for ED MOS Logic LSI. - Takeshi Tokuda; Kaoru Okazaki; Kazuhiro Sakashita; Isao Ohkura; Tatsuya Enomoto (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1983)

A Hierarchical Standard Cell Approach for Custom VLSI Design. - Takeshi Tokuda; Jiro Korematsu; Osamu Tomisawa; Sotoju Asai; Isao Ohkura; Tatsuya Enomoto (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1984)

A 32-bit Microprocessor Based on the TRON Architecture: Design of the GMICRO/100. - Tom Shimizu; Toyohiko Yoshida; Yuichi Saito; Masahito Matsuo; Tatsuya Enomoto (COMPCON, 1988)

32-bit microprocessors based on the TRON specification. - Ken Sakamura; Tatsuya Enomoto (Microprocess. Microsystems, 1989)