A 4500 MIPS/W, 86 µA Resume-Standby, 11 µA Ultra-Standby Application Processor for 3G Cellular Phones. - Makoto Ishikawa; Tatsuya Kamei; Yuki Kondo; Masanao Yamaoka; Yasuhisa Shimazaki; Motokazu Ozawa; Saneaki Tamaki; Mikio Furuyama; Tadashi Hoshi; Fumio Arakawa; Osamu Nishii; Kenji Hirose; et al. (IEICE Trans. Electron., 2005)

SH-X: an embedded processor core for consumer appliances. - Fumio Arakawa; Makoto Ishikawa; Yuki Kondo; Tatsuya Kamei; Motokazu Ozawa; Osamu Nishii; Toshihiro Hattori (SIGARCH Comput. Archit. News, 2005)

SH-X: An embedded processor core for consumer appliances. - Fumio Arakawa; Makoto Ishikawa; Yuki Kondo; Tatsuya Kamei; Osamu Nishii; Toshihiro Hattori (J. Embed. Comput., 2006)

Development of processor cores for digital consumer appliances. - Fumio Arakawa; Tetsuya Yamada; Takashi Okada; Makoto Ishikawa; Yuki Kondo; Motokazu Ozawa; Tomoyuki Kodama; Osamu Nishii; Toshihiro Hattori; Tatsuya Kamei; Junichi Nishimoto; Shinichi Yoshioka (Syst. Comput. Jpn., 2006)

Embedded SoC Resource Manager to Control Temperature and Data Bandwidth. - Makoto Saen; Kenichi Osada; Satoshi Misaka; Tetsuya Yamada; Yoshitaka Tsujimoto; Yuki Kondo; Tatsuya Kamei; Yutaka Yoshida; Ei Nagahama; Yusuke Nitta; Takayasu Ito; Tadashi Kameyama; et al. (ISSCC, 2007)

A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption. - Yutaka Yoshida; Tatsuya Kamei; Kiyoshi Hayase; Shinichi Shibahara; Osamu Nishii; Toshihiro Hattori; Atsushi Hasegawa; Masashi Takada; Naohiko Irie; Kunio Uchiyama; Toshihiko Odaka; Kiwamu Takada; et al. (ISSCC, 2007)

A 65nm Single-Chip Application and Dual-Mode Baseband Processor with Partial Clock Activation and IP-MMU. - Masao Naruse; Tatsuya Kamei; Toshihiro Hattori; Takahiro Irita; Kenichi Nitta; Takao Koike; Shinichi Yoshioka; Koji Ohno; Masahito Saigusa; Minoru Sakata; Yukio Kodama; Yuji Arai; et al. (ISSCC, 2008)

Heterogeneous Multi-Core Architecture That Enables 54x AAC-LC Stereo Encoding. - Hiroaki Shikano; Masaki Ito; Masafumi Onouchi; Takashi Todaka; Takanobu Tsunoda; Tomoyuki Kodama; Kunio Uchiyama; Toshihiko Odaka; Tatsuya Kamei; Ei Nagahama; Manabu Kusaoke; Yusuke Nitta; et al. (IEEE J. Solid State Circuits, 2008)

A 65nm dual-mode baseband and multimedia application processor SoC with advanced power and memory management. - Tatsuya Kamei; Tetsuhiro Yamada; Takao Koike; Masayuki Ito; Takahiro Irita; Kenichi Nitta; Toshihiro Hattori; Shinichi Yoshioka (ASP-DAC, 2009)

A 65 nm Single-Chip Application and Dual-Mode Baseband Processor With Partial Clock Activation and IP-MMU. - Masayuki Ito; Kenichi Nitta; Koji Ohno; Masahito Saigusa; Masaki Nishida; Shinichi Yoshioka; Takahiro Irita; Takao Koike; Tatsuya Kamei; Teruyoshi Komuro; Toshihiro Hattori; Yasuhiro Arai; et al. (IEEE J. Solid State Circuits, 2009)

An Efficient and Accurate Time Step Control Method for Power Device Transient Simulation Utilizing Dominant Time Constant Approximation. - Shigetaka Kumashiro; Tatsuya Kamei; Akira Hiroki; Kazutoshi Kobayashi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

4.2 A 12nm Autonomous-Driving Processor with 60.4TOPS, 13.8TOPS/W CNN Executed by Task-Separated ASIL D Control. - Katsushige Matsubara; Hanno Lieske; Motoki Kimura; Atsushi Nakamura; Manabu Koike; Kazuaki Terashima; Shun Morikawa; Yoshihiko Hotta; Takahiro Irita; Seiji Mochizuki; Hiroyuki Hamasaki; Tatsuya Kamei (ISSCC, 2021)

A 12-nm Autonomous Driving Processor With 60.4 TOPS, 13.8 TOPS/W CNN Executed by Task-Separated ASIL D Control. - Katsushige Matsubara; Hanno Lieske; Motoki Kimura; Atsushi Nakamura; Manabu Koike; Shun Morikawa; Yoshihiko Hotta; Takahiro Irita; Seiji Mochizuki; Hiroyuki Hamasaki; Tatsuya Kamei (IEEE J. Solid State Circuits, 2022)

A 33kDMIPS 6.4W Vehicle Communication Gateway Processor Achieving 10Gbps/W Network Routing, 40ms CAN Bus Start-Up and 1.4mW Standby Power. - Kenichi Shimada; Keiichiro Sano; Kazuki Fukuoka; Hiroshi Morita; Masayuki Daito; Tatsuya Kamei; Hiroyuki Hamasaki; Yasuhisa Shimazaki (ISSCC, 2023)