A 30-ns 256-Mb DRAM with a multidivided array structure. - Tadahiko Sugibayashi; Toshio Takeshima; Isao Naritake; Tatsuya Matano; Hiroshi Takada; Yoshiharu Aimoto; Koichiro Furuta; Mamoru Fujita; Takanori Saeki; Hiroshi Sugawara; Tatsunori Murotani; Naoki Kasai; et al. (IEEE J. Solid State Circuits, 1993)

A 2.5-ns clock access, 250-MHz, 256-Mb SDRAM with synchronous mirror delay. - Takanori Saeki; Yuji Nakaoka; Mamoru Fujita; Akihito Tanaka; Kyoichi Nagata; Kenichi Sakakibara; Tatsuya Matano; Yukio Hoshino; Kazutaka Miyano; Satoshi Isa; Shigeyuki Nakazawa; Eiichiro Kakehashi; et al. (IEEE J. Solid State Circuits, 1996)

A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer. - Tatsuya Matano; Yasuhiro Takai; Tsugio Takahashi; Yuusuke Sakito; Isamu Fujii; Yoshihiro Takaishi; Hiroki Fujisawa; Shuichi Kubouchi; Seiji Narui; Koji Arai; Makoto Morino; Masayuki Nakamura; et al. (IEEE J. Solid State Circuits, 2003)

1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1Gb SDRAM with dual-clock input-latch scheme and hybrid multi-oxide output buffer. - Hiroki Fujisawa; Masayuki Nakamura; Yasuhiro Takai; Yasuji Koshikawa; Tatsuya Matano; Seiji Narui; Narikazu Usuki; Chiaki Dono; Shinichi Miyatake; Makoto Morino; Koji Arai; Shuichi Kubouchi; et al. (IEEE J. Solid State Circuits, 2005)

A novel on-chip voltage generator for low voltage DRAMs and PRAMs. - Tatsuya Matano; Koji Sato; Kiyoshi Nakai; Isamu Asano (CICC, 2009)