Nonvolatile Memory With Extremely Low-Leakage Indium-Gallium-Zinc-Oxide Thin-Film Transistor. - Hiroki Inoue; Takanori Matsuzaki; Shuhei Nagatsuka; Yutaka Okazaki; Toshinari Sasaki; Kousei Noda; Daisuke Matsubayashi; Takahiko Ishizu; Tatsuya Onuki; Atsuo Isobe; Yutaka Shionoiri; Kiyoshi Kato; et al. (IEEE J. Solid State Circuits, 2012)

Embedded SRAM and Cortex-M0 core with backup circuits using a 60-nm crystalline oxide semiconductor for power gating. - Hikaru Tamura; Kiyoshi Kato; Takahiko Ishizu; Tatsuya Onuki; Wataru Uesugi; Takuro Ohmaru; Kazuaki Ohshima; Hidetomo Kobayashi; Seiichi Yoneda; Atsuo Isobe; Naoaki Tsutsui; Suguru Hondo; et al. (COOL Chips, 2014)

A 32-bit CPU with zero standby power and 1.5-clock sleep/2.5-clock wake-up achieved by utilizing a 180-nm C-axis aligned crystalline In-Ga-Zn oxide transistor. - Atsuo Isobe; Hikaru Tamura; Kiyoshi Kato; Takuro Ohmaru; Wataru Uesugi; Takahiko Ishizu; Tatsuya Onuki; Kazuaki Ohshima; Takanori Matsuzaki; Atsushi Hirose; Yasutaka Suzuki; Naoaki Tsutsui; et al. (VLSIC, 2014)

16.9 A 128kb 4b/cell nonvolatile memory with crystalline In-Ga-Zn oxide FET using Vt, cancel write method. - Takanori Matsuzaki; Tatsuya Onuki; Shuhei Nagatsuka; Hiroki Inoue; Takahiko Ishizu; Yoshinori Ieda; Naoto Yamade; Hidekazu Miyairi; Masayuki Sakakura; Tomoaki Atsumi; Yutaka Shionoiri; Kiyoshi Kato; et al. (ISSCC, 2015)

Embedded memory and ARM Cortex-M0 core using 60-nm C-axis aligned crystalline indium-gallium-zinc oxide FET integrated with 65-nm Si CMOS. - Tatsuya Onuki; Wataru Uesugi; Hikaru Tamura; Atsuo Isobe; Yoshinori Ando; Satoru Okamoto; Kiyoshi Kato; Tri Rung Yew; Chen Bin Lin; J. Y. Wu; Chi Chang Shuai; Shao Hui Wu; et al. (VLSI Circuits, 2016)

Embedded Memory and ARM Cortex-M0 Core Using 60-nm C-Axis Aligned Crystalline Indium-Gallium-Zinc Oxide FET Integrated With 65-nm Si CMOS. - Tatsuya Onuki; Wataru Uesugi; Atsuo Isobe; Yoshinori Ando; Satoru Okamoto; Kiyoshi Kato; Tri Rung Yew; J. Y. Wu; Chi Chang Shuai; Shao Hui Wu; James Myers; Klaus Doppler; et al. (IEEE J. Solid State Circuits, 2017)

Soft- and Hard-Error Radiation Reliability of 228 KB $3 mathrm{T}+1 mathrm{C}$ Oxide Semiconductor Memory. - H. Takahashi; Y. Okamoto; Toshiki Hamada; Yusuke Komura; S. Watanabe; K. Tsuda; H. Sawai; Takanori Matsuzaki; Yoshinori Ando; Tatsuya Onuki; Hitoshi Kunitake; Shunpei Yamazaki; et al. (IRPS, 2023)

Two-Dimensionally Arranged Display Drivers Achieved by OS/Si Structure. - Yusuke Komura; Shoki Miyata; Yuki Okamoto; Yuki Tamatsukuri; Hiroki Inoue; Toshihiko Saito; Munehiro Kozuma; Hidetomo Kobayashi; Tatsuya Onuki; Yuichi Yanagisawa; Toshihiko Takeuchi; Yutaka Okazaki; et al. (VLSI Technology and Circuits, 2023)

1Mbit 1T1C 3D DRAM with Monolithically Stacked One Planar FET and Two Vertical FET Heterogeneous Oxide Semiconductor layers over Si CMOS. - Yuki Okamoto; Yusuke Komura; Toshiki Mizuguchi; Toshihiko Saito; Minato Ito; K. Kimura; Tatsuya Onuki; Yoshinori Ando; Hiromi Sawai; Tsutomu Murakawa; Hitoshi Kunitake; Takanori Matsuzaki; et al. (VLSI Technology and Circuits, 2023)

Heterogeneous Oxide Semiconductor FETs Comprising Planar FET and Vertical Channel FETs Monolithically Stacked on Si CMOS, Enabling 1-Mbit 3D DRAM. - Hiraki Inoue; Takeya Hirose; Toshiki Mizuguchi; Yusuke Komura; Toshihiko Saito; Minato Ito; Kiyotaka Kimura; Tatsuya Onuki; Yoshinori Ando; Hiromi Sawai; Tsutomu Murakawa; Hitoshi Kunitake; et al. (IMW, 2024)