Partially-Parallel LDPC Decoder Based on High-Efficiency Message-Passing Algorithm. - Kazunori Shimizu; Tatsuyuki Ishikawa; Takeshi Ikenaga; Satoshi Goto; Nozomu Togawa (ICCD, 2005)

High-throughput decoder for low-density parity-check code. - Tatsuyuki Ishikawa; Kazunori Shimizu; Takeshi Ikenaga; Satoshi Goto (ASP-DAC, 2006)

A parallel LSI architecture for LDPC decoder improving message-passing schedule. - Kazunori Shimizu; Tatsuyuki Ishikawa; Nozomu Togawa; Takeshi Ikenaga; Satoshi Goto (ISCAS, 2006)

Partially-Parallel LDPC Decoder Achieving High-Efficiency Message-Passing Schedule. - Kazunori Shimizu; Tatsuyuki Ishikawa; Nozomu Togawa; Takeshi Ikenaga; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

Power-Efficient LDPC Decoder Architecture Based on Accelerated Message-Passing Schedule. - Kazunori Shimizu; Tatsuyuki Ishikawa; Nozomu Togawa; Takeshi Ikenaga; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)