An efficient 2-D DWT architecture via resource cycling. - Tay-Jyi Lin; Chein-Wei Jen (ISCAS (4), 2001)

CASCADE - configurable and scalable DSP environment. - Tay-Jyi Lin; Chein-Wei Jen (ISCAS (4), 2002)

An Efficient VLIW DSP Architecture for Baseband Processing. - Tay-Jyi Lin; Chin-Chi Chang; Chen-Chia Lee; Chein-Wei Jen (ICCD, 2003)

Performance evaluation of ring-structure register file in multimedia applications. - Tay-Jyi Lin; Chin-Chi Chang; Tsung-Hsun Yang; Yu-Ming Chang; Chien-Hung Lin; Chen-Chia Lee; Hung-Yueh Lin; Chein-Wei Jen (ICME, 2003)

Coefficient optimization for area-effective multiplier-less FIR filters. - Tay-Jyi Lin; Tsung-Hsun Yang; Chein-Wei Jen (ICME, 2003)

Area-effective FIR filter design for multiplier-less implementation. - Tay-Jyi Lin; Tsung-Hsun Yang; Chein-Wei Jen (ISCAS (5), 2003)

A compact DSP core with static floating-point unit & its microcode generation. - Tay-Jyi Lin; Hung-Yueh Lin; Chie-Min Chao; Chih-Wei Liu; Chein-Wei Jen (ACM Great Lakes Symposium on VLSI, 2004)

Static floating-point unit with implicit exponent tracking for embedded DSP. - Hung-Yueh Lin; Tay-Jyi Lin; Chie-Min Chao; Yen-Chin Liao; Chih-Wei Liu; Chein-Wei Jen (ISCAS (2), 2004)

A unified processor architecture for RISC & VLIW DSP. - Tay-Jyi Lin; Chie-Min Chao; Chia-Hsien Liu; Pi-Chen Hsiao; Shin-Kai Chen; Li-Chun Lin; Chih-Wei Liu; Chein-Wei Jen (ACM Great Lakes Symposium on VLSI, 2005)

Architecture for area-efficient 2-D transform in H.264/AVC. - Yu-Ting Kuo; Tay-Jyi Lin; Chih-Wei Liu; Chein-Wei Jen (ICME, 2005)

Pipelining technique for energy-aware datapaths. - Wei-Sheng Huang; Tay-Jyi Lin; Shih-Hao Ou; Chih-Wei Liu; Chein-Wei Jen (ISCAS (2), 2005)

Hierarchical instruction encoding for VLIW digital signal processors. - Chia-Hsien Liu; Tay-Jyi Lin; Chie-Min Chao; Pi-Chen Hsiao; Li-Chun Lin; Shin-Kai Chen; Chao-Wei Huang; Chih-Wei Liu; Chein-Wei Jen (ISCAS (4), 2005)

A 52mW 1200MIPS compact DSP for multi-core media SoC. - Shih-Hao Ou; Tay-Jyi Lin; Chao-Wei Huang; Yu-Ting Kuo; Chie-Min Chao; Chih-Wei Liu; Chein-Wei Jen (ASP-DAC, 2006)

Programmable FIR filter with adder-based computing engine. - Yu-Ting Kuo; Tay-Jyi Lin; Yi Cho; Chih-Wei Liu; Chein-Wei Jen (ISCAS, 2006)

A Compact DSP Core with Static Floating-Point Arithmetic. - Tay-Jyi Lin; Hung-Yueh Lin; Chie-Min Chao; Chih-Wei Liu; Chih-Wei Jen (J. VLSI Signal Process., 2006)

Single-Issue 1500MIPS Embedded DSP with Ultra Compact Codes. - Li-Chun Lin; Shih-Hao Ou; Tay-Jyi Lin; Siang-Den Deng; Chih-Wei Liu (ASP-DAC, 2007)

Design of ANSI S1.11 Filter Bank for Digital Hearing Aids. - Yu-Ting Kuo; Tay-Jyi Lin; Yueh-Tai Li; Wei-Han Chang; Chih-Wei Liu; Shuenn-Tsong Young (ICECS, 2007)

Rapid C to FPGA Prototyping with Multithreaded Emulation Engine. - Shin-Kai Chen; Bing-Shiun Wang; Tay-Jyi Lin; Chih-Wei Liu (ISCAS, 2007)

Latency-Tolerant Virtual Cluster Architecture for VLIW DSP. - Pi-Chen Hsiao; Tay-Jyi Lin; Chih-Wei Liu; Chein-Wei Jen (ISCAS, 2007)

Multithreaded coprocessor interface for multi-core multimedia SoC. - Shih-Hao Ou; Tay-Jyi Lin; Xiang Sheng Deng; Zhi Hong Zhuo; Chih-Wei Liu (ASP-DAC, 2008)

Cycle Stealing and Channel Management for On-Chip Networks. - Jwo-An Lin; Yung-Chou Tsai; Tay-Jyi Lin; Yarsun Hsu (HPCC, 2008)

Complexity-effective auditory compensation for digital hearing aids. - Yu-Ting Kuo; Tay-Jyi Lin; Wei-Han Chang; Yueh-Tai Li; Chih-Wei Liu; Shuenn-Tsong Young (ISCAS, 2008)

Improving datapathutilization of programmable DSP with composite functional units. - Shih-Hao Ou; Yi Cho; Tay-Jyi Lin; Chih-Wei Liu (ISCAS, 2008)

Design and Implementation of a High-Performance and Complexity-Effective VLIW DSP for Multimedia Applications. - Tay-Jyi Lin; Shin-Kai Chen; Yu-Ting Kuo; Chih-Wei Liu; Pi-Chen Hsiao (J. Signal Process. Syst., 2008)

Ultra low-power ANSI S1.11 filter bank for digital hearing aids. - Yu-Ting Kuo; Tay-Jyi Lin; Yueh-Tai Li; Chou-Kun Lin; Chih-Wei Liu (ASP-DAC, 2009)

Parallel object detection on multicore platforms. - Shin-Kai Chen; Tay-Jyi Lin; Chih-Wei Liu (SiPS, 2009)

RunAssert: A non-intrusive run-time assertion for parallel programs debugging. - Chi-Neng Wen; Shu-Hsuan Chou; Tien-Fu Chen; Tay-Jyi Lin (DATE, 2010)

Collaborative voltage scaling with online STA and variable-latency datapath. - Tay-Jyi Lin; Pi-Chen Hsiao; Chi-Hung Lin; Shu-Chang Kuo; Chou-Kun Lin; Yu-Ting Kuo; Chih-Wei Liu; Yuan-Hua Chu (ACM Great Lakes Symposium on VLSI, 2010)

Hierarchical memory scheduling for multimedia MPSoCs. - Ye-Jyun Lin; Chia-Lin Yang; Tay-Jyi Lin; Jiao-Wei Huang; Naehyuck Chang (ICCAD, 2010)

Complexity-effective dynamic range compression for digital hearing aids. - Kuo-Chiang Chang; Yu-Ting Kuo; Tay-Jyi Lin; Chih-Wei Liu (ISCAS, 2010)

Improving energy efficiency of functional units by exploiting their data-dependent latency. - Shih-Hao Ou; Yen-Cheng Lin; Tay-Jyi Lin; Chih-Wei Liu (ISCAS, 2010)

Design and Implementation of Low-Power ANSI S1.11 Filter Bank for Digital Hearing Aids. - Yu-Ting Kuo; Tay-Jyi Lin; Yueh-Tai Li; Chih-Wei Liu (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Complexity-Aware Quantization and Lightweight VLSI Implementation of FIR Filters. - Yu-Ting Kuo; Tay-Jyi Lin; Chih-Wei Liu (EURASIP J. Adv. Signal Process., 2011)

Hierarchical circuit-switched NoC for multicore video processing. - Shu-Hsuan Chou; Chien-Chih Chen; Chi-Neng Wen; Tien-Fu Chen; Tay-Jyi Lin (Microprocess. Microsystems, 2011)

Parallel Architecture Core (PAC) - the First Multicore Application Processor SoC in Taiwan Part I: Hardware Architecture & Software Development Tools. - David Chih-Wei Chang; Tay-Jyi Lin; Chung-Ju Wu; Jenq Kuen Lee; Yuan-Hua Chu; An-Yeu Wu (J. Signal Process. Syst., 2011)

Complexity-effective Hilbert-Huang transform (HHT) IP for embedded real-time applications. - Shyang-Chyun Chen; Chao-Chuan Chen; Wen-Chi Guo; Tay-Jyi Lin; Ching-Wei Yeh (ASP-DAC, 2012)

Energy-efficient RISC design with on-demand circuit-level timing speculation. - Tay-Jyi Lin; Yu-Ting Kuo; Yu-Jung Tsai; Ting-Yu Shyu; Yuan-Hua Chu (ASP-DAC, 2012)

A smart stream controller for efficient implementation of streaming applications on the heterogeneous multicore processor. - Shih-Hao Ou; Che-Wei Yeh; Tay-Jyi Lin; Chih-Wei Liu (ISCAS, 2012)

A 4R/2W Register File Design for UDVS Microprocessors in 65-nm CMOS. - Pei-Yao Chang; Tay-Jyi Lin; Jinn-Shyan Wang; Yen-Hsiang Yu (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS. - Tay-Jyi Lin; Cheng-An Chien; Pei-Yao Chang; Ching-Wen Chen; Po-Hao Wang; Ting-Yu Shyu; Chien-Yung Chou; Shien-Chun Luo; Jiun-In Guo; Tien-Fu Chen; Gene C. H. Chuang; Yuan-Hua Chu; et al. (ISSCC, 2013)

Variation-aware and adaptive-latency accesses for reliable low voltage caches. - Po-Hao Wang; Wei-Chung Cheng; Yung-Hui Yu; Tang-Chieh Kao; Chi-Lun Tsai; Pei-Yao Chang; Tay-Jyi Lin; Jinn-Shyan Wang; Tien-Fu Chen (VLSI-SoC, 2013)

Low power fixed-latency DSP accelerator with autonomous minimum energy tracking (AMET). - Chung-Hsun Huang; Wei-Jen Chen; Keng-Jui Chang; Yi-Hsuan Ting; Keng-Chang Hsu; Yu-Fu Pan; Chao-Chun Chen; Yuan-Hua Chu; Tay-Jyi Lin; Jinn-Shyan Wang (Hot Chips Symposium, 2014)

Maintaining color fidelity for dual-shot HDR imaging. - Chingwei Yeh; Chen-Yao Tsai; Tay-Jyi Lin; Jiun-In Guo (ICCE-TW, 2014)

Low-cost low-power droop-voltage-aware delay-fault-prevention designs for DVS caches. - Pei-Yuan Chou; I-Chen Wu; Jai-Wei Lin; Xuan-Yu Lin; Tien-Fu Chen; Tay-Jyi Lin; Jinn-Shyan Wang (ASICON, 2015)

System-Level Performance and Power Optimization for MPSoC: A Memory Access-Aware Approach. - Ye-Jyun Lin; Chia-Lin Yang; Jiao-Wei Huang; Tay-Jyi Lin; Chih-Wen Hsueh; Naehyuck Chang (ACM Trans. Embed. Comput. Syst., 2015)

A low complexity edge-preserved image compression algorithm for LCD overdrive. - Chao-Yang Chang; Chung-Hsun Huang; Hui-Fu Chen; Chingwei Yeh; Yuan-Sun Chu; Tay-Jyi Lin (GCCE, 2016)

Variable-length VLIW encoding for code size reduction in embedded processors. - Ting-Yu Shyu; Bo-Yu Su; Tay-Jyi Lin; Chingwei Yeh; Jinn-Shyan Wang; Tien-Fu Chen (SoCC, 2016)

Overoptimistic voltage scaling in pre-error AVS systems and learning-based alleviation. - Yi-Hsuan Ting; Chih-Yang Wang; Yu-Sian Chang; Tay-Jyi Lin; Shih-Chieh Chang; Jinn-Shyan Wang (SoCC, 2016)

Cross-matching caches: Dynamic timing calibration and bit-level timing-failure mask caches to reduce timing discrepancies with low voltage processors. - Po-Hao Wang; Shang-Jen Tsai; Rizal Tanjung; Tay-Jyi Lin; Jinn-Shyan Wang; Tien-Fu Chen (Integr., 2016)

Zero-Counting and Adaptive-Latency Cache Using a Voltage-Guardband Breakthrough for Energy-Efficient Operations. - Po-Hao Wang; Wei-Chung Cheng; Yung-Hui Yu; Tang-Chieh Kao; Chi-Lun Tsai; Pei-Yao Chang; Tay-Jyi Lin; Jinn-Shyan Wang; Tien-Fu Chen (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Speculative Lookahead for Energy-Efficient Microprocessors. - Tay-Jyi Lin; Ting-Yu Shyu (IEEE Trans. Very Large Scale Integr. Syst., 2016)

An all-n-type dynamic adder for ultra-low-leakage IoT devices. - Ya-Bei Fang; Pei-Yuan Chou; Bo-Hao Chen; Tay-Jyi Lin; Jinn-Shyan Wang (ASICON, 2017)

Approximate Distributed Arithmetic for Variable-Latency Table Lookup. - Yi-Hsuan Ting; Tay-Jyi Lin; Cheng-Chun Chang; Chih-Chien Hu; Chingwei Yeh; Jinn-Shyan Wang (NGCAS, 2017)

ULV-Turbo Cache for an Instantaneous Performance Boost on Asymmetric Architectures. - Po-Hao Wang; Yung-Chen Chien; Shang-Jen Tsai; Xuan-Yu Lin; Rizal Tanjung; Yi-Sian Lin; Shu-Wei Syu; Tay-Jyi Lin; Jinn-Shyan Wang; Tien-Fu Chen (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Near-Threshold CORDIC Design with Dynamic Circuitry for Long-Standby IoT Applications. - Pei-Yuan Chou; Ya-Bei Fang; Bo-Hao Chen; Chien-Tung Liu; Tay-Jyi Lin; Jinn-Shyan Wang (SoCC, 2018)

A Low-Area, Low-Power, and Low-Leakage Error-Detecting Latch for Timing-Error Resilient System Designs. - Chien-Tung Liu; Zhe-Wei Chang; Shih-Nung Wei; Jinn-Shyan Wang; Tay-Jyi Lin (SoCC, 2018)

A 0.21V 40nm NAND-ROM for IoT Sensing Systems with Long Standby Periods. - Jinn-Shyan Wang; Cheng-Xin Xue; Chien-Tung Liu; Tay-Jyi Lin (ISCAS, 2020)

A 40nm CMOS SoC for Real-Time Dysarthric Voice Conversion of Stroke Patients. - Tay-Jyi Lin; Chen-Zong Liao; You-Jia Hu; Wei-Cheng Hsu; Zheng-Xian Wu; Shao-Yu Wang; Chun-Ming Huang; Ying-Hui Lai; Chingwei Yeh; Jinn-Shyan Wang (ASP-DAC, 2022)

Force-Sensing Intelligent Vise for Cutting Dynamics Monitoring in Machining. - Po-Han Chen; Tay-Jyi Lin; Chingwei Yeh; Pei-Zen Chang; Wei-Chang Li (SENSORS, 2023)

A 16 nm 140 TOPS/W 5 μJ/Inference Keyword Spotting Engine Based on 1D-BCNN. - Tay-Jyi Lin; Yi-Hsuan Ting; Meng-Ze Hsu; Kuan-Han Lin; Chung-Ming Huang; Fu-Cheng Tsai; Shyh-Shyuan Sheu; Shih-Chieh Chang; Chingwei Yeh; Jinn-Shyan Wang (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A 40-nm 13.88-TOPS/W FC-DNN Engine for 16-bit Intelligent Audio Processing Featuring Weight-Sharing and Approximate Computing. - Tay-Jyi Lin; Ze Li; Yun-Cheng Chen; Chien-Tung Liu; Tien-Fu Chen; Jinn-Shyan Wang (HCS, 2024)

Performance Evaluation of MEMS Vibration Sensors for Throat Microphones. - Che-Yu Hsu; Po-Han Chen; Ting-Yi Chen; Shang-Yu Lin; Ching-Jen Wang; Chingwei Yeh; Tay-Jyi Lin; Pei-Zen Chang; Wei-Chang Li (IEEE SENSORS, 2024)

Efficient Inference of Transformers on Bare-Metal Devices with RISC-V Vector Processors. - Yi-Xuan Huang; Po-Han Huang; Juin-Ming Lu; Tay-Jyi Lin; Tien-Fu Chen (NewCAS, 2024)