Multi-gigahertz arbitrary timing generator and data pattern serializer/formatter. - David C. Keezer; Te-Hui Chen; Carl Edward Gray; Hyun Woo Choi; Sungyeol Kim; Seongkwan Lee; Hosun Yoo (ITC, 2012)

Practical methods for extending ATE to 40 and 50Gbps. - David C. Keezer; Carl Edward Gray; Te-Hui Chen; Ashraf Majid (ITC, 2013)

An FPGA-based ATE extension module for low-cost multi-GHz memory test. - David C. Keezer; Te-Hui Chen; Thomas Moon; D. T. Stonecypher; Abhijit Chatterjee; Hyun Woo Choi; Sungyeol Kim; Hosun Yoo (ETS, 2015)

An Ultra-High-Speed Test Module and FPGA-Based Development Platform. - Te-Hui Chen; David C. Keezer (ATS, 2016)

A 40Gbps economic extension board and FPGA-based testing platform. - Te-Hui Chen; David C. Keezer (ETS, 2016)

Concurrent Multi-Channel Crosstalk Jitter Characterization Using Coprime Period Channel Stimulus. - Nicholas Tzou; Debesh Bhatta; Xian Wang 003; Te-Hui Chen; Sen-Wen Hsiao; Barry J. Muldrey; Hyun Woo Choi; Abhijit Chatterjee (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

High-speed, low cost test platform using FPGA technology. - Te-Hui Chen (2017)