Fully testable PLA design with minimal extra input. - Che W. Chiou; Ted C. Yang (EURO-DAC, 1990)

Modeling and Performance Evaluation of RISC/B Processor. - Yang-Yueh Chen; Ted C. Yang (ICSI, 1990)

Universal syndrome-testable design of programmable logic arrays. - Ted C. Yang; Che W. Chiou (Integr., 1990)

Testable PLA design with minimal overheads. - Ted C. Yang; Che W. Chiou (Integr., 1990)

Parallel modular multiplication with table look-up. - Che Wun Chiou; Ted C. Yang (Int. J. Comput. Math., 1998)

A Dynamic Fault-Tolerant Mesh Architecture. - Jyh-Ming Huang; Ted C. Yang (IPPS/SPDP Workshops, 1999)

A Compiler-Based Speculative Execution Scheme for ILP Enhancement. - L. Wang; Ted C. Yang (J. Inf. Sci. Eng., 2000)

Multidestination Multicast Communication Based on Hierarchical Block Rings. - Jyh-Ming Huang; Ted C. Yang (PDCS, 2001)

On the Boosting of Instruction Scheduling by Renaming. - L. Wang; Ted C. Yang (J. Supercomput., 2001)

Tensor Product Modeling of Fault Tolerant Multiprocessor Architectures. - Jyh-Ming Huang; Chua-Huang Huang; Ted C. Yang (ICPADS, 2002)

A Fast Base-K Logarithm with Redundant Representation. - Che Wun Chiou; Ted C. Yang (J. Inf. Sci. Eng., 2005)